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The main SoC is labeled <code>CXD5315GG</code>. The design is a stacked SoC with the SDRAM found in the same chip as the processor cores. Toshiba details their "[http://www.toshiba-components.com/ASIC/SiP.html Stacked Chip SOC]" on their site. From reversing code and looking at FCC documentation, it appears that the internal name of the chip is "Kermit."
+
The PS Vita main SoC, nicknamed Kermit, is manufactured by Toshiba. The design is a stacked SoC with the SDRAM found in the same chip as the processor cores. Toshiba details their "[http://www.toshiba-components.com/ASIC/SiP.html Stacked Chip SOC]" on their site.
   −
More information can be found at [http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/sonys-ps-vita-uses-chip-on-chip-sip-3d-but-not-3d/ Chipworks].
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More information can be found at [https://web.archive.org/web/20150425204407/http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/sonys-ps-vita-uses-chip-on-chip-sip-3d-but-not-3d/ Chipworks].
    
[[File:T9ML7MBG-S.png|thumb|From FCC application 712137]]
 
[[File:T9ML7MBG-S.png|thumb|From FCC application 712137]]
 
According to the internal photos found in the [https://apps.fcc.gov/oetcf/eas/reports/ViewExhibitReport.cfm?mode=Exhibits&RequestTimeout=500&calledFromFrame=N&application_id=712137&fcc_id=AK8PCH1101A FCC filings], it appears that an earlier version of the chip is labeled <code>T9ML7MBG-S</code>. This does not appear to be a standard model and is likely custom designed in partnership with Sony Computer Entertainment Japan. It is possible that Sony used [http://www.toshiba-components.com/ASIC/index.html this service] from Toshiba in their design process which is why the prototype demonstrated in the FCC filing shows a Toshiba chip..
 
According to the internal photos found in the [https://apps.fcc.gov/oetcf/eas/reports/ViewExhibitReport.cfm?mode=Exhibits&RequestTimeout=500&calledFromFrame=N&application_id=712137&fcc_id=AK8PCH1101A FCC filings], it appears that an earlier version of the chip is labeled <code>T9ML7MBG-S</code>. This does not appear to be a standard model and is likely custom designed in partnership with Sony Computer Entertainment Japan. It is possible that Sony used [http://www.toshiba-components.com/ASIC/index.html this service] from Toshiba in their design process which is why the prototype demonstrated in the FCC filing shows a Toshiba chip..
    +
== Variants ==
 +
There are multiple known variants of Kermit. SoC revision is readable from [[Pervasive#.22SoC_revision.22|a ScePervasiveMisc register]].
 +
 +
In the following table, a value of <code>0x000XXXYZ</code> will be named <code>Kermit [depends on XXX] ESYrZ</code>.
 +
 +
{| class="wikitable"
 +
|+ Known Kermit revisions
 +
|-
 +
! Kermit revision !! SoC model number !! Unit model number !! Notes
 +
|-
 +
| Kermit ES4r2 || CXD5315GG || PCH-1xxx, VTE-10xx || Retail unit, ?512MiB LPDDR2?
 +
|-
 +
| Kermit ES4r2 || CXD5315GG-1 || PDEL-10xx || TOOL, ?1.5GiB LPDDR2?
 +
|-
 +
| Kermit ES1 || ??? || DEM revision before DEM-3000G || CPU is Cortex-A8, GPU is SGX541MP, ?no CDRAM? -  only ES1r0 and ES1r1 should exist
 +
|-
 +
| Kermit ES2 || ??? || DEM-3000G ?to DEM-3000H? || CPU is Cortex-A9, GPU is SGX543MP4+
 +
|-
 +
| Kermit ES3 || ??? || ?DEM-3000JEC, some DEM-3000K/J? ||
 +
|-
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| Kermit ES4r? || T9ML7MBG-S || CEM-3000VD1 || Units used for [https://fccid.io/AK8PCH1001A PCH-1001 FCC certification] and [https://fccid.io/AK8PCH1101A PCH-1101 FCC certification] uses this chip. Most likely ES4, probably ES4r2.
 +
|-
 +
| Kermit15 ES1r5 || CXD5316GG || PCH-20xx || Name comes from <code>KERMIT15</code> string in [[SceSysStateMgr]] - might stand for "Kermit 1.5". Some late version of this chip has the <code>AU_CODEC_IC_CONEXANT</code>.
 +
|}
 +
 +
== Schema ==
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 +
This is for DevKit. Retail and TestKit are different:
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* The DevKit carries 1 GiB of LPDDR2 DRAM (usually referred to as the "main memory"). The retail unit and TestKit carry 512 MiB of LPDDR2 DRAM.
 +
 +
[[File:PSVita custom SoC schema.png]]
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 +
== CPU ==
 +
 +
See [[Main_Processor]].
 +
 +
== GPU ==
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 +
See [[SGX543]].
 +
 +
== LPDDR2 DRAM (main memory) ==
 +
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* The retail unit and TestKit carry 512 MiB of LPDDR2 DRAM.
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 +
* The DevKit carries 1 GiB of LPDDR2 DRAM (usually referred to as the "main memory").
 +
 +
=== Trace Memory ===
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 +
The DevKit mounts 512 MiB of LPDDR2 DRAM for performance analysis.
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 +
This memory is for storing performance measurement data referred by a performance analyzer (Razor for PlayStation®Vita) or runtime libraries.
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 +
== Custom DRAM ==
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 +
The DevKit carries 128 MiB of custom DRAM (usually referred to as the "video memory"). ?Retail/TesKit too?
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 +
== Codec Engine ==
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 +
Codec Engine is a media processor configured with multiple cores. Only the specific processing of the specific libraries is processed through Codec Engine instead of CPU.
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 +
== Other Key Units and Bus Configuration ==
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 +
As other key units, the custom SoC includes the features below:
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* Direct Memory Access Controllers (DMAC)
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* AVC Decoder
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* A video out interface
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* Misc input/outputs interface etc.
    
== Pinout ==
 
== Pinout ==
   −
[[File:kermit-bga.png|thumb|600px|Source is a [[Media:Kermit_bga.numbers.zip|iWork Numbers file]].]]
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[[File:kermit-bga.png|600px|Source is a [[Media:Kermit_bga.numbers.zip|iWork Numbers file]].]]
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The pinout is mostly reversed from the [http://wololo.net/talk/viewtopic.php?p=402775 PCB delayer] and is based off of PCH-1XXX on the IRS-002 board. It may not include some pins only used in other Vita models.
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The pinout is mostly reversed from the [http://wololo.net/talk/viewtopic.php?p=402775 PCB delayer] and is based off of PCH-1XXX on the IRS-002 board. It may not include some pins only used in other PS Vita models.
    
=== UART ===
 
=== UART ===
Line 36: Line 104:  
| RX5 || A17 || UART5 receive
 
| RX5 || A17 || UART5 receive
 
|}
 
|}
      
=== USB ===
 
=== USB ===
Line 56: Line 123:  
|-
 
|-
 
| D- UDC || AB30 || Multiconnector USB D  (client, OTG maybe supported)
 
| D- UDC || AB30 || Multiconnector USB D  (client, OTG maybe supported)
 +
|-
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| USB VBUS || AA29 || Also goes to SN99057
 
|}
 
|}
   Line 105: Line 174:  
| DAT7 1 || W2 || Gamecard DAT7 (unused)
 
| DAT7 1 || W2 || Gamecard DAT7 (unused)
 
|-
 
|-
| CLK 2 || T1 || Wifi/BT clock
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| CLK 2 || T1 || Wlan/Bt clock
 
|-
 
|-
| CMD 2 || Q1 || Wifi/BT CMD
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| CMD 2 || Q1 || Wlan/Bt CMD
 
|-
 
|-
| DAT0 2 || S1 || Wifi/BT DAT0
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| DAT0 2 || S1 || Wlan/Bt DAT0
 
|-
 
|-
| DAT1 2 || S2 || Wifi/BT DAT1
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| DAT1 2 || S2 || Wlan/Bt DAT1
 
|-
 
|-
| DAT2 2 || R1 || Wifi/BT DAT2
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| DAT2 2 || R1 || Wlan/Bt DAT2
 
|-
 
|-
| DAT3 2 || R2 || Wifi/BT DAT3
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| DAT3 2 || R2 || Wlan/Bt DAT3
 
|-
 
|-
 
| Vddq || U1 || SDIO voltage regulation
 
| Vddq || U1 || SDIO voltage regulation
Line 121: Line 190:  
| Vddq || U2 || SDIO voltage regulation
 
| Vddq || U2 || SDIO voltage regulation
 
|}
 
|}
      
=== MS ===
 
=== MS ===
   −
See [[SceMsif]].
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See [[MSIF Registers]].
    
{| class='wikitable'
 
{| class='wikitable'
Line 144: Line 212:  
| DAT3 || AC10 || Memorycard DAT3
 
| DAT3 || AC10 || Memorycard DAT3
 
|}
 
|}
      
=== MIPI DSI ===
 
=== MIPI DSI ===
Line 165: Line 232:  
| D1- 0 || G1 || Internal display data 1 lane
 
| D1- 0 || G1 || Internal display data 1 lane
 
|}
 
|}
      
=== MIPI CSI ===
 
=== MIPI CSI ===
Line 189: Line 255:  
|}
 
|}
    +
=== SPI ===
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=== SPI ===
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[[File:vita-syscon-spi.png|thumb|400px|SPI0 (Syscon) trace. Termination resistor under the shield.]]
    
See [[SPI Registers]].
 
See [[SPI Registers]].
Line 205: Line 272:  
| MOSI 0 || Z14 || Syscon SPI input
 
| MOSI 0 || Z14 || Syscon SPI input
 
|-
 
|-
| CS 1 || AA12 || Accelerometer IC SPI chip select
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| CS 1 || AA12 || Motion (accelerometer IC) SPI chip select
 
|-
 
|-
| SCK 1 || Z13 || Accelerometer IC SPI clock
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| SCK 1 || Z13 || Motion (accelerometer IC) SPI clock
 
|-
 
|-
| MISO 1 || AA13 || Accelerometer IC SPI output
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| MISO 1 || AA13 || Motion (accelerometer IC) SPI output
 
|-
 
|-
| MOSI 1 || Z12 || Accelerometer IC SPI input
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| MOSI 1 || Z12 || Motion (accelerometer IC) SPI input
 
|-
 
|-
 
| CS 2 || AA10 || P1P40167 clock synthesizer SPI chip select
 
| CS 2 || AA10 || P1P40167 clock synthesizer SPI chip select
Line 221: Line 288:  
| MOSI 2 || Z10 || P1P40167 clock synthesizer SPI input
 
| MOSI 2 || Z10 || P1P40167 clock synthesizer SPI input
 
|}
 
|}
      
=== GPIO ===
 
=== GPIO ===
Line 238: Line 304:  
| Syscon || A20 || To syscon
 
| Syscon || A20 || To syscon
 
|-
 
|-
| Motion || E25 || To accelerometer IC
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| Motion || E25 || To Motion (accelerometer IC)
 
|-
 
|-
| Motion || A26 || To accelerometer IC
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| Motion || A26 || To Motion (accelerometer IC)
 
|-
 
|-
 
| Camera || E21 || To camera
 
| Camera || E21 || To camera
Line 268: Line 334:  
| eMMC RST_N || B26 || RST_N of eMMC
 
| eMMC RST_N || B26 || RST_N of eMMC
 
|}
 
|}
      
=== I2C ===
 
=== I2C ===
Line 298: Line 363:  
| pullup? || AB29 || Goes to a pullup resistor?
 
| pullup? || AB29 || Goes to a pullup resistor?
 
|-
 
|-
| Syscon || AA9 || Goes to syscon
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| Wlan/Bt || AA9 || Goes to Wlan/Bt SoC
|-
  −
| rst? || AA29 || Goes to PMIC, maybe rst_n?
   
|-
 
|-
 
| pad W4 || X4 || Goes to pad, connects with W4
 
| pad W4 || X4 || Goes to pad, connects with W4
Line 308: Line 371:  
| pullup X27 || W27 || Pullup resistor to X27
 
| pullup X27 || W27 || Pullup resistor to X27
 
|-
 
|-
| rst? || X29 || Goes near PMIC, might be reset
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| || X29 || Goes near PMIC
 
|-
 
|-
| rst? || X30 || Goes near PMIC, might be reset
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| || X30 || Goes near PMIC
 
|-
 
|-
 
| pad M7 || U29 || Connects to M7 with a passive
 
| pad M7 || U29 || Connects to M7 with a passive
Line 341: Line 404:  
|}
 
|}
   −
 
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=== Clocks/Reset ===
=== Clocks ===
      
See [[Pervasive]].
 
See [[Pervasive]].
Line 355: Line 417:  
| 27M || A11 || 27MHz, suspected input to main PLL
 
| 27M || A11 || 27MHz, suspected input to main PLL
 
|-
 
|-
| 48M || AC27 || 48MHz, suspected USB related
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| 48M || AC27 || 48MHz, SD controller
 
|-
 
|-
| 37M || C30 || 37MHz
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| 37M || C30 || 37MHz, suspected main clock
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|-
 +
| RST_N || B9 || Held for 20ms on startup by Syscon, 100K pulldown
 
|}
 
|}
      
=== Power ===
 
=== Power ===
    
Different power domains are numbered. Some voltages are unknown.
 
Different power domains are numbered. Some voltages are unknown.
[[File:vita-caps.png|thumb|200px|Decoupling capacitors for some major power domains are shown.]]
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[[File:vita-caps.png|thumb|400px|Decoupling capacitors for some major power domains are shown.]]
    
{| class='wikitable'
 
{| class='wikitable'
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