SGX543: Difference between revisions
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Line 611: | Line 611: | ||
! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0 | ! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0 | ||
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| || | | colspan="1" style="text-align:center;" | || colspan="3" style="text-align:center;" | opcode2 || colspan="4" style="text-align:center;" | | ||
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| x || || || || 1 || x || x || x | | x || || || || 1 || x || x || x |
Revision as of 21:17, 9 February 2018
Instruction set
It looks like instructions are 8 bytes long. Roughly speaking - first 4 bytes contain opcode and addressing mode. Second 4 bytes contain operands encoding.
Bit encoding used in this reference.
value | meaning |
---|---|
0 | bit clear |
1 | bit set |
x | dont care |
? | unknown |
0x00000000 - 0x08000000
Instructions: mad
Encoding:
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Fields:
data_format:
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predicate:
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Examples:
mad.f32 p0 mad.f32 !p0 mad.f32 Pn mad.f32 mad.f16 p0 mad.f16 !p0 mad.f16 Pn mad.f16
0x08000000 - 0x10000000
Instructions: mul.f32
Encoding:
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Fields:
predicate:
2 | 1 | 0 | value |
---|---|---|---|
0 | 0 | 0 | |
0 | 0 | 1 | p0 |
0 | 1 | 0 | p1 |
0 | 1 | 1 | p2 |
1 | 0 | 0 | !p0 |
1 | 0 | 1 | !p1 |
1 | 1 | 0 | !p2 |
1 | 1 | 1 | Pn |
Examples:
mul.f32 p0 mul.f32 p1 mul.f32 p2 mul.f32 !p0 mul.f32 !p1 mul.f32 !p2 mul.f32 Pn mul.f32
0x10000000 - 0x18000000
Instructions: mul.f16
Encoding:
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Fields:
predicate:
2 | 1 | 0 | value |
---|---|---|---|
0 | 0 | 0 | |
0 | 0 | 1 | p0 |
0 | 1 | 0 | p1 |
0 | 1 | 1 | p2 |
1 | 0 | 0 | !p0 |
1 | 0 | 1 | !p1 |
1 | 1 | 0 | !p2 |
1 | 1 | 1 | Pn |
Examples:
mul.f16 p0 mul.f16 p1 mul.f16 p2 mul.f16 !p0 mul.f16 !p1 mul.f16 !p2 mul.f16 Pn mul.f16
0x18000000 - 0x20000000
Instructions: dot.f32, mad.f32
Encoding:
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Fields:
opcode2:
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predicate:
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Examples:
dot.f32 p0 dot.f32 p1 dot.f32 p2 dot.f32 !p0 dot.f32 !p1 dot.f32 !p2 dot.f32 Pn dot.f32 mad.f32 p0 mad.f32 p1 mad.f32 p2 mad.f32 !p0 mad.f32 !p1 mad.f32 !p2 mad.f32 Pn mad.f32
0x20000000 - 0x28000000
Instructions: dot, mov, rsq, rcp, exp, log
Encoding:
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Notes:
Having bit 3 in byte 2 set to 0 produces invalid instruction
Fields:
data_format:
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predicate:
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opcode2 (depends on op_sel):
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dot.f32 p0 dot.f32 !p0 dot.f32 Pn dot.f32 mov.f32 p0 mov.f32 !p0 mov.f32 Pn mov.f32 rsq.f32 p0 rsq.f32 !p0 rsq.f32 Pn rsq.f32 rcp.f32 p0 rcp.f32 !p0 rcp.f32 Pn rcp.f32 exp.f32 p0 exp.f32 !p0 exp.f32 Pn exp.f32 log.f32 p0 log.f32 !p0 log.f32 Pn log.f32 dot.f16 p0 dot.f16 !p0 dot.f16 Pn dot.f16 mov.f16 p0 mov.f16 !p0 mov.f16 Pn mov.f16 rsq.f16 p0 rsq.f16 !p0 rsq.f16 Pn rsq.f16 rcp.f16 p0 rcp.f16 !p0 rcp.f16 Pn rcp.f16 exp.f16 p0 exp.f16 !p0 exp.f16 Pn exp.f16 log.f16 p0 log.f16 !p0 log.f16 Pn log.f16
0x28000000 - 0x30000000
Instructions: dot, mov, rsq, rcp
Encoding:
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0x30000000 - 0x38000000
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0x38000000 - 0x40000000
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0x40000000 - 0x48000000
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0x48000000 - 0x50000000
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0x50000000 - 0x58000000
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0x58000000 - 0x60000000
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0x60000000 - 0x68000000
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0x68000000 - 0x70000000
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0x70000000 - 0x78000000
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0x78000000 - 0x80000000
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0x80000000 - 0x88000000
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0x88000000 - 0x90000000
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0x90000000 - 0x98000000
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0x98000000 - 0xA0000000
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0xA0000000 - 0xA8000000
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0xA8000000 - 0xB0000000
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0xB0000000 - 0xB8000000
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0xB8000000 - 0xC0000000
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0xC0000000 - 0xC8000000
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0xC8000000 - 0xD0000000
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0xD0000000 - 0xD8000000
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0xD8000000 - 0xE0000000
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0xE0000000 - 0xE8000000
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0xE8000000 - 0xF0000000
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0xF0000000 - 0xF8000000
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0xF8000000 - 0xFF000000
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