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Revision as of 13:33, 25 February 2018
Instruction set
General Info
It looks like instructions are 8 bytes long. Roughly speaking - first 4 bytes contain opcode and addressing mode. Second 4 bytes contain operands encoding.
Bit encoding used in this reference:
value | meaning |
---|---|
0 | bit clear |
1 | bit set |
x | dont care |
? | unknown |
see reference |
Predicates
Not sure about predicates yet, but they are used to mask execution of certain instructions.
Notation is the following:
<predicate> <instruction>
For example:
!p0 mad.f32
To reduce amount of examples - they are not listed with predicates.
It is assumed that all predicates are applicable to all instructions in the group unless opposite is indicated.
Operands
Currently - only known form of operands is registers.
Instructions may have up to four operands specified.
In this documentation they will be encoded as:
<op0> <op1> <op2> <op3>
Registers
- pa - primary attribute register. 32 bit long.
- sa - secondary attribute register. 32 bit long.
- o - output register. 32 bit long.
- r - temporary register. 32 bit long.
- i - internal register. 128 bit long.
Register Selector RS2
This encoding uses 2 bits to encode register type.
selector is encoded as:
1 | 0 | meaning |
---|---|---|
0 | 0 | r |
0 | 1 | o |
1 | 0 | pa |
1 | 1 | sa |
Note that internal registers are not encoded - they are reserved in Register R6
Register Selector Indexable RSI2
This encoding uses 2 bits to encode register type.
selector is encoded as:
1 | 0 | meaning |
---|---|---|
0 | 0 | r |
0 | 1 | o |
1 | 0 | pa |
1 | 1 | index<N> mode |
When index<N> mode is used - there has to be another field that encodes index expression with Register Index Offset RIO6
The way that index expression is buit:
<reg>[index1 * 2 + <offset>]
Example:
r[index1 * 2 + 8]
Register R6
This encoding uses 6 bits to encode register index.
register is encoded as:
5 | 4 | 3 | 2 | 1 | 0 | index |
---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 2 |
... | ... | ... | ... | ... | ... | |
1 | 1 | 1 | 0 | 1 | 0 | 116 |
1 | 1 | 1 | 0 | 1 | 1 | 118 |
1 | 1 | 1 | 1 | 0 | 0 | i0 (reserved) |
1 | 1 | 1 | 1 | 0 | 1 | i1 (reserved) |
1 | 1 | 1 | 1 | 1 | 0 | i2 (reserved) |
1 | 1 | 1 | 1 | 1 | 1 | i3 (reserved) |
index is calculated as: value * 2
Register expression is built as:
<reg><index>
Example:
sa68
Specific type of register can be selected with Register Selector RS2
For destination operand op0 specific type of register can be selected with Register Selector Indexable RSI2
Last 4 values are reserved for internal registers i0, i1, i2, i3
Register Index Offset RIO6
5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|
rt | offset | ||||
rt is encoded as Register Selector RS2
offset is calculated as: value * 2
offset is encoded as:
3 | 2 | 1 | 0 | offset |
---|---|---|---|---|
0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 1 | 2 |
... | ... | ... | ... | ... |
1 | 1 | 1 | 0 | 28 |
1 | 1 | 1 | 1 | 30 |
Register Swizzle RSWZ2
This encoding uses 2 bits to encode the mask.
channel is encoded as:
1 | 0 | meaning |
---|---|---|
0 | 0 | x |
0 | 1 | y |
1 | 0 | z |
1 | 1 | w |
swizzle expression is built as:
<reg><index>.<swizzle>
Example:
r22.x
Immediates
Immediate IMM6
Some operands may act as immediate values which are encoded using 6 bits.
Constants
Constant CNST6
Some operands may act as constant values which are encoded using 6 bits.
Constants are taken from table below.
Constants differ in 32 and 16 bit mode.
Table for 16 bit mode does not have accurate values.
f32 mode:
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f16 mode:
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Modifier and dest data format
At the moment it is not known which of the data format fields is dest and which is source.
This is the reason why term modifier is mixed with term dest data format.
0x00000000 - 0x08000000
Instructions
mad
Encoding
Higher 4 bytes
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Lower 4 bytes
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Notes
- x bits do not affect instruction or operands. might affect something else?
- what do index<N> mean. are these registers or something?
- is there a flag that allows to switch constant table? there is a second table that exists.
- looks like there is functionality to switch sign of index expression
- still need Register Swizzle RSWZ2? there are too many modes for swizzling
- probably can move swizzling to generic section. if other instructions use same encodings.
Fields (instruction)
data_format:
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predicate:
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Fields (operands)
- swz_alt_op1 - does not have effect on its own. can be used together with swz_mask32 or swz_mask16 to change op1 swizzle. does not have effect with swz_en.
when both swz_mask32 or swz_mask16 and swz_en are enabled - changes op1 swizzle differently.
- alt_opt0 - alter opt0. this bit can be combined with opt0 to produce the following modes for op0:
alt_opt0 | opt0 | value | details | |
---|---|---|---|---|
1 | 0 | 0 | sa | |
1 | 0 | 1 | {} | op0 encodes CNST6. applicable only when swizzling is enabled. |
1 | 1 | 0 | index0 | |
1 | 1 | 1 | index2 mode | op0 encodes RIO6. opt0 encodes RSI2 |
- abs_op1 - add abs modifier to op1. example:
abs(pa38)
- alt_opt2 - alter opt2. this bit can be combined with opt2 to produce the following modes for op2:
alt_opt2 | opt2 | value | details | |
---|---|---|---|---|
1 | 0 | 0 | index1 mode | op2 encodes RIO6. opt2 encodes RSI2 |
1 | 0 | 1 | {} | op2 encodes CNST6. applicable only when swizzling is enabled. |
1 | 1 | 0 | immediate | op2 encodes IMM6 |
1 | 1 | 1 | index2 mode | op2 encodes RIO6. opt2 encodes RSI2 |
- alt_opt3 - alter opt3. this bit can be combined with opt3 to produce the following modes for op3:
alt_opt3 | opt3 | value | details | |
---|---|---|---|---|
1 | 0 | 0 | index1 mode | op3 encodes RIO6. opt3 encodes RSI2 |
1 | 0 | 1 | {} | op3 encodes CNST6. applicable only when swizzling is enabled. |
1 | 1 | 0 | immediate | op3 encodes IMM6 |
1 | 1 | 1 | index2 mode | op3 encodes RIO6. opt3 encodes RSI2 |
- swz_alt_op3 - does not have effect on its own. can be used together with swz_mask32 or swz_mask16 to change op3 swizzle. does not have effect with swz_en.
when both swz_mask32 or swz_mask16 and swz_en are enabled - changes op3 swizzle differently.
- op3_swz - op3 swizzle encoded with Register Swizzle RSWZ2. does not have effect on its own. must be used with swz_en or swz_mask32 or swz_mask16 or both.
- swz_alt_op2 - does not have effect on its own. can be used together with swz_mask32 or swz_mask16 to change op2 swizzle. does not have effect with swz_en.
when both swz_mask32 or swz_mask16 and swz_en are enabled - changes op2 swizzle differently.
- swz_mask16 - masks first two channels for swizzles that are controlled by op1_swz, op2_swz, op3_swz. applies only to mad.f16
- swz_mask32 - masks first channel for swizzles that are controlled by op1_swz, op2_swz, op3_swz. applies only to mad.f32
- swz_en - enables usage of swizzling that is controlled by op1_swz, op2_swz, op3_swz. swizzle of op0 can be changed only with swz_en or swz_mask32 or swz_mask16 and does not have dedicated field.
- abs_op2 - add abs modifier to op2. example:
abs(pa20)
- neg_op2 - negate op2. example:
-pa86
- abs_op3 - add abs modifier to op3. example:
abs(r20)
- neg_op3 - negate op3. example:
-r86
- opt1 - when enabled - selects pa register type. when disabled - selects r register type.
- opt0 - type of operand op0, encoded with Register Selector Indexable RSI2
- opt2 - type of operand op2, encoded with Register Selector RS2. or Register Selector Indexable RSI2 if specified in alt_opt2.
- opt3 - type of operand op3, encoded with Register Selector RS2. or Register Selector Indexable RSI2 if specified in alt_opt3.
- op0 - op0 encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in opt0.
or with Register Index Offset RIO6 using index2 mode if specified in alt_opt0. or with CNST6.
- op2_swz - op2 swizzle encoded with Register Swizzle RSWZ2. does not have effect on its own. must be used with swz_en or swz_mask32 or swz_mask16 or both.
- op1_swz - op1 swizzle encoded with Register Swizzle RSWZ2. does not have effect on its own. must be used with swz_en or swz_mask32 or swz_mask16 or both.
- op1 - encoded with Register R6
- op2 - encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in alt_opt2.
or with Register Index Offset RIO6 using index2 mode if specified in alt_opt2. or IMM6 if specified in alt_opt2. or with CNST6.
- op3 - encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in alt_opt3.
or with Register Index Offset RIO6 using index2 mode if specified in alt_opt3. or IMM6 if specified in alt_opt3. or with CNST6.
Constants
Specific operand may be used as float constant. This can be achived with following groups of bits:
- alt_opt0, opt0, op0
- alt_opt2, opt2, op2
- alt_opt3, opt3, op3
Float constants can only be used when swizzling is enabled for particular operand. Consider checking sections Swizzles_f32 and Swizzles_f16.
Constants are taken from tables Constants.
Constants differ between 32 and 16 bit mode.
Constants are same for each operand.
When particular channel is masked with swizzing (swz_mask32 or swz_mask16) - this channel is assigned to 0.0 instead of constant.
Swizzles f32
There are multiple combinations available, controlled by:
- swizzle fields: op1_swz, op2_swz, op3_swz
- control bits: swz_en, swz_mask32, swz_alt_op1, swz_alt_op2, swz_alt_op3
operand 0 | operand 1 | operand 2 | operand 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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operand 0 | operand 1 | operand 2 | operand 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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operand 0 | operand 1 | operand 2 | operand 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Swizzles f16
There are multiple combinations available, controlled by:
- swizzle fields: op1_swz, op2_swz, op3_swz
- control bits: swz_en, swz_mask16, swz_alt_op1, swz_alt_op2, swz_alt_op3
operand 0 | operand 1 | operand 2 | operand 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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operand 0 | operand 1 | operand 2 | operand 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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operand 0 | operand 1 | operand 2 | operand 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Examples
mad.f32 mad.f16
0x08000000 - 0x10000000
Instructions: mul.f32
Encoding:
Higher 4 bytes
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Lower 4 bytes
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Fields: predicate:
Examples: mul.f32 0x10000000 - 0x18000000Instructions: mul.f16 Encoding:
Fields: predicate:
Examples: mul.f16 0x18000000 - 0x20000000Instructions: dot.f32, mad.f32 Encoding:
Fields:
Examples: dot.f32 mad.f32 0x20000000 - 0x28000000Instructions: dot, mov, rsq, rcp, exp, log Encoding:
Notes: Having bit 3 in byte 2 set to 0 produces invalid instruction Fields:
opcode2 (depends on op_sel):
Examples: dot.f32 mov.f32 rsq.f32 rcp.f32 exp.f32 log.f32 dot.f16 mov.f16 rsq.f16 rcp.f16 exp.f16 log.f16 0x28000000 - 0x30000000Instructions: dot, mov, rsq, rcp Encoding:
Notes: Having bit 3 in byte 2 set to 0 produces invalid instruction Fields:
opcode2:
Examples: dot.f32 mov.f32 rsq.f32 rcp.f32 dot.f16 mov.f16 rsq.f16 rcp.f16 0x30000000 - 0x38000000Instructions: rcp, rsq, log, exp Encoding:
Notes:
Fields:
Examples: rcp.f32 rsq.f32 log.f32 exp.f32 rcp.f32.fx10 rsq.f32.fx10 log.f32.fx10 exp.f32.fx10 rcp.f16.f32 rsq.f16.f32 log.f16.f32 exp.f16.f32 rcp.f16.fx10 rsq.f16.fx10 log.f16.fx10 exp.f16.fx10 rcp.fx10.f32 rsq.fx10.f32 log.fx10.f32 exp.fx10.f32 rcp.fx10 rsq.fx10 log.fx10 exp.fx10 0x38000000 - 0x40000000Instructions: mov, cmov, cmov8 Encoding:
Notes:
Fields:
Examples: mov.i8 mov.i16 mov.i32 mov.fx10 mov.f16 mov.f32 cmov.eqzero.i8 cmov.eqzero.i16 cmov.eqzero.i32 cmov.eqzero.fx10 cmov.eqzero.f16 cmov.eqzero.f32 cmov8.eqzero.i8 cmov8.eqzero.i16 cmov8.eqzero.i32 cmov8.eqzero.fx10 cmov8.eqzero.f16 cmov8.eqzero.f32 cmov.ltzero.i8 cmov.ltzero.i16 cmov.ltzero.i32 cmov.ltzero.fx10 cmov.ltzero.f16 cmov.ltzero.f32 cmov8.ltzero.i8 cmov8.ltzero.i16 cmov8.ltzero.i32 cmov8.ltzero.fx10 cmov8.ltzero.f16 cmov8.ltzero.f32 0x40000000 - 0x48000000Instructions: pack, (mov) Encoding:
Notes: when furthermore instruction mnemonic shall be replaced to Fields:
Examples: mov.u8 pack.s16.u8 pack.u8.s8 pack.s16.s8 pack.u8.o8 pack.s16.o8 pack.u8.u16 pack.s16.u16 pack.u8.s16 mov.s16 pack.u8.f16 pack.s16.f16 pack.u8.f32 pack.s16.f32 0x48000000 - 0x50000000Instructions: this group only contains illegal instructions Encoding:
0x50000000 - 0x58000000Instructions: and.u32 Encoding:
Fields: predicate:
Examples: and.u32 0x58000000 - 0x60000000Instructions: xor.u32 Encoding:
Fields: predicate:
Examples: xor.u32 0x60000000 - 0x68000000Instructions: shl.u32 Encoding:
Fields: predicate:
Examples: shl.u32 0x68000000 - 0x70000000Instructions: shr.u32 Encoding:
Fields: predicate:
Examples: shr.u32 0x70000000 - 0x78000000Instructions: rlp.u32 Encoding:
Fields: predicate:
Examples: rlp.u32 0x78000000 - 0x80000000Instructions: this group only contains illegal instructions Encoding:
0x80000000 - 0x88000000Instructions: add.fx8 Encoding:
Fields: predicate:
Examples: add.fx8 0x88000000 - 0x90000000Instructions: add.fx8, sub.fx8 Encoding:
Notes: Having bits 2, 3 in byte 2 set to 1 produces invalid instruction Fields:
Examples: add.fx8 sub.fx8 0x90000000 - 0x98000000Instructions: add.fx8, sub.fx8, min.fx8, max.fx8 Encoding:
Notes: Having bit 0 in byte 2 set to 1 produces invalid instruction Fields:
Examples: add.fx8 sub.fx8 min.fx8 max.fx8 0x98000000 - 0xA0000000Instructions: mad.u8 Encoding:
Fields:
Examples: mad.u8 mad.sat.u8 0xA0000000 - 0xA8000000Instructions: mad Encoding:
Fields:
Examples: mad.u16 mad.u16.sat mad.i16 mad.i16.sat 0xA8000000 - 0xB0000000Instructions: mad Encoding:
Fields:
Examples: mad.u32 mad.u32.sat mad.i32 mad.i32.sat 0xB0000000 - 0xB8000000Instructions: this group only contains illegal instructions Encoding:
0xB8000000 - 0xC0000000Instructions: this group only contains illegal instructions Encoding:
0xC0000000 - 0xC8000000Instructions: this group only contains illegal instructions Encoding:
0xC8000000 - 0xD0000000Instructions: mad.u8 Encoding:
Fields:
Examples: mad.u8 mad.sat.u8 0xD0000000 - 0xD8000000Instructions: mad Encoding:
Notes: Having bit 5 in byte 1 set to 1 produces invalid instruction Fields:
Examples: mad.u32.s0 mad.i32.s0 mad.u32.s1 mad.i32.s1 0xD8000000 - 0xE0000000Instructions: this group only contains illegal instructions Encoding:
0xE0000000 - 0xE8000000Instructions: tex Encoding:
Fields:
Examples: tex1D tex1D.f16 tex1D.f32 tex1D.minp tex1D.minp.f16 tex1D.minp.f32 tex1DBias tex1DBias.f16 tex1DBias.f32 tex1DBias.minp tex1DBias.minp.f16 tex1DBias.minp.f32 tex1DReplace tex1DReplace.f16 tex1DReplace.f32 tex1DReplace.minp tex1DReplace.minp.f16 tex1DReplace.minp.f32 tex1DGrad tex1DGrad.f16 tex1DGrad.f32 tex1DGrad.minp tex1DGrad.minp.f16 tex1DGrad.minp.f32 tex2D tex2D.f16 tex2D.f32 tex2D.minp tex2D.minp.f16 tex2D.minp.f32 tex2DBias tex2DBias.f16 tex2DBias.f32 tex2DBias.minp tex2DBias.minp.f16 tex2DBias.minp.f32 tex2DReplace tex2DReplace.f16 tex2DReplace.f32 tex2DReplace.minp tex2DReplace.minp.f16 tex2DReplace.minp.f32 tex2DGrad tex2DGrad.f16 tex2DGrad.f32 tex2DGrad.minp tex2DGrad.minp.f16 tex2DGrad.minp.f32 texCube texCube.f16 texCube.f32 texCube.minp texCube.minp.f16 texCube.minp.f32 texCubeBias texCubeBias.f16 texCubeBias.f32 texCubeBias.minp texCubeBias.minp.f16 texCubeBias.minp.f32 texCubeReplace texCubeReplace.f16 texCubeReplace.f32 texCubeReplace.minp texCubeReplace.minp.f16 texCubeReplace.minp.f32 texCubeGrad texCubeGrad.f16 texCubeGrad.f32 texCubeGrad.minp texCubeGrad.minp.f16 texCubeGrad.minp.f32 0xE8000000 - 0xF0000000Instructions: lda32, ldl32, ldt32 Encoding:
Notes:
Fields:
Examples: lda32 ldl32 ldt32 lda32.fetch1 lda32.fetch2 lda32.fetch3 lda32.fetch4 lda32.fetch5 lda32.fetch6 lda32.fetch7 lda32.fetch8 lda32.fetch9 lda32.fetch10 lda32.fetch11 lda32.fetch12 lda32.fetch13 lda32.fetch14 lda32.fetch15 lda32.fetch16 ldl32.fetch1 ldl32.fetch2 ldl32.fetch3 ldl32.fetch4 ldl32.fetch5 ldl32.fetch6 ldl32.fetch7 ldl32.fetch8 ldl32.fetch9 ldl32.fetch10 ldl32.fetch11 ldl32.fetch12 ldl32.fetch13 ldl32.fetch14 ldl32.fetch15 ldl32.fetch16 ldt32.fetch1 ldt32.fetch2 ldt32.fetch3 ldt32.fetch4 ldt32.fetch5 ldt32.fetch6 ldt32.fetch7 ldt32.fetch8 ldt32.fetch9 ldt32.fetch10 ldt32.fetch11 ldt32.fetch12 ldt32.fetch13 ldt32.fetch14 ldt32.fetch15 ldt32.fetch16 0xF0000000 - 0xF8000000Instructions: sta32, stl32, stt32 Encoding:
Notes:
Fields:
Examples: sta32 stl32 stt32 sta32.fetch1 sta32.fetch2 sta32.fetch3 sta32.fetch4 sta32.fetch5 sta32.fetch6 sta32.fetch7 sta32.fetch8 sta32.fetch9 sta32.fetch10 sta32.fetch11 sta32.fetch12 sta32.fetch13 sta32.fetch14 sta32.fetch15 sta32.fetch16 stl32.fetch1 stl32.fetch2 stl32.fetch3 stl32.fetch4 stl32.fetch5 stl32.fetch6 stl32.fetch7 stl32.fetch8 stl32.fetch9 stl32.fetch10 stl32.fetch11 stl32.fetch12 stl32.fetch13 stl32.fetch14 stl32.fetch15 stl32.fetch16 stt32.fetch1 stt32.fetch2 stt32.fetch3 stt32.fetch4 stt32.fetch5 stt32.fetch6 stt32.fetch7 stt32.fetch8 stt32.fetch9 stt32.fetch10 stt32.fetch11 stt32.fetch12 stt32.fetch13 stt32.fetch14 stt32.fetch15 stt32.fetch16 0xF8000000 - 0xFF000000Notes: this instruction group is much more complex than others so description is given in form of "glued" truth tables instead of independent truth tables. predicate 000Instructions: Encoding:
Fields: opcode2:
Examples: predicate 001Instructions: Encoding
Notes: predicate does not apply to all instructions Fields opcode2:
Examples: predicate 010Instructions: Encoding:
Notes: predicate does not apply to all instructions Fields opcode2
Examples: predicate 011Instructions: Encoding
Notes: predicate does not apply to all instructions Fields opcode2
Examples: predicate 100Instructions: Encoding
Notes: predicate does not apply to all instructions Fields opcode2:
Examples: predicate 101Instructions: Encoding
Notes: predicate does not apply to all instructions Fields opcode2:
Examples: predicate 110Instructions: Encoding
Notes: predicate does not apply to all instructions Fields opcode2:
Examples: predicate 111Instructions: Encoding
Notes: predicate does not apply to all instructions Fields opcode2:
Examples: |