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MMIO Interfaces
Name
|
Physical address
|
SceDsi0Reg
|
0xE5050000
|
SceDsi1Reg
|
0xE5060000
|
Registers
Engine
|
Offset
|
Size
|
Description
|
RGB output
|
0x004
|
4
|
bits[1:0]: Video mode (0 = Progressive, 0b11 = Interlaced)
|
0x008
|
4
|
bits[31:0]: (htotal * clocks_per_pixel) >> 1
|
0x00C
|
4
|
bits[28:16]: vtotal , bits[12:0]: (vtotal + 1) >> 1
|
0x010
|
4
|
bits[31:0]: 0x10001
|
0x014
|
4
|
bits[31:16]: ((HSW + HBP) * clocks_per_pixel) >> 1 , bits[15:0]: (((HSW + HBP + hact) * clocks_per_pixel) >> 1) + 1
|
0x01C
|
4
|
bits[28:16]: VSW + VBP - 1 , bits[12:0]: ((vtotal + 1) >> 1) - VFP
|
0x020
|
4
|
bits[28:16]: VSW + VBP + ((vtotal - 1) >> 1) , bits[12:0]: vtotal - VFP + 1
|
0x024
|
4
|
bits[31:16]: (HSW * clocks_per_pixel) >> 1 , bit[0]: 1
|
0x02C
|
4
|
bits[31:0]: 0x10001
|
0x030
|
4
|
bits[28:16]: VSW , bits[15:0]: (htotal * clocks_per_pixel) >> 1
|
0x034
|
4
|
bits[28:16]: (vtotal + 1) >> 1 , bits[15:0]: ((htotal * clocks_per_pixel) >> 2) + 1
|
0x038
|
4
|
bits[28:16]: VSW + ((vtotal + 1) >> 1) , bits[15:0]: (htotal * clocks_per_pixel) >> 2
|
0x03C
|
4
|
bits[31:0]: 1
|
0x040
|
4
|
bits[28:16]: ((vtotal + 1) >> 1) + (VSW + VBP) - 8 , bits[15:0]: (VSW + VBP) - 8
|
0x04C
|
4
|
bits[31:16]: current Vcount , bits[15:0]: ??
|
0x050
|
4
|
Interrupts ack/clear (read = triggered interrupts, write = clear interrupt)
|
0x054
|
4
|
Interrupt enable mask (bit 1 = some interrupt)
|
0x05C
|
4
|
Progressive |
Interlaced
|
0x10001 |
bits[28:16]: (vtotal + 1) >> 1 , bits[15:0]: 1
|
|
0x060
|
4
|
Progressive |
Interlaced
|
bits[28:16]: VSW + VBP , bits[15:0]: 1 |
bits[28:16]: VSW + VBP + ((vtotal - 1) >> 1) , bits[15:0]: 1
|
|
RGB-to-DSI PHY Rx
|
0x410
|
4
|
DSI_STATUS. DSI Command read FIFO status (bit 5 = Read FIFO empty)
|
0x414
|
4
|
DSI_INT. Some sort of status. Ready/busy?
|
0x430
|
4
|
DSICMD_RXFIFO. DSI Command read FIFO
|
RGB-to-DSI PHY Tx
|
0x500
|
4
|
DSI_CONFW?. DSI Command FIFO
|
0x504
|
4
|
DSI_RESET?. DSI Command FIFO packet size (in multiples of 32b)
|
0x50C
|
4
|
DSI_INT_CLR
|
0x510
|
4
|
Another command FIFO (used to write the packet for command reads)
|
0x51C
|
4
|
Transfer control. bit[0]: Transfer direction (0 = read, 1 = write). Seems to be some kind of SPI/I2C interface
|
Unknown
|
0x838
|
4
|
DSI auto clock configuration (1 = only HS clock, 0 = auto gate when data in LP)
|