Difference between revisions of "SPI Registers"
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| (7 intermediate revisions by the same user not shown) | |||
| Line 11: | Line 11: | ||
| 0xE0A10000 | | 0xE0A10000 | ||
|- | |- | ||
| − | | SceSpi2Reg (SceOled) | + | | SceSpi2Reg (SceOled, SceLcd) |
| 0xE0A20000 | | 0xE0A20000 | ||
|} | |} | ||
| Line 21: | Line 21: | ||
! Size | ! Size | ||
! Description | ! Description | ||
| + | |- | ||
| + | | 0x00 | ||
| + | | 4 | ||
| + | | Read FIFO | ||
|- | |- | ||
| 0x04 | | 0x04 | ||
| 4 | | 4 | ||
| − | | FIFO | + | | Write FIFO |
| + | |- | ||
| + | | 0x08 | ||
| + | | 4 | ||
| + | | Configuration | ||
| + | |- | ||
| + | | 0x0C | ||
| + | | 4 | ||
| + | | Interrupt control? | ||
|- | |- | ||
| 0x10 | | 0x10 | ||
| 4 | | 4 | ||
| Start transfer (write 0b1), cancel transfer(write 0b0), transfer busy (reads bit0 = 0)? | | Start transfer (write 0b1), cancel transfer(write 0b0), transfer busy (reads bit0 = 0)? | ||
| + | |- | ||
| + | | 0x14 | ||
| + | | 4 | ||
| + | | ?? | ||
|- | |- | ||
| 0x18 | | 0x18 | ||
| Line 40: | Line 56: | ||
| 0x28 | | 0x28 | ||
| 4 | | 4 | ||
| − | | | + | | Number of available bytes to read from the FIFO |
|- | |- | ||
| 0x2C | | 0x2C | ||
| 4 | | 4 | ||
| − | | | + | | Number of pending bytes in the write the FIFO (maximum = 0x7F) |
|} | |} | ||
Revision as of 18:19, 11 November 2019
MMIO Interfaces
| Name | Physical address |
|---|---|
| SceSpi0Reg (SceSyscon) | 0xE0A00000 |
| SceSpi1Reg (SceMotionDev) | 0xE0A10000 |
| SceSpi2Reg (SceOled, SceLcd) | 0xE0A20000 |
Registers
| Offset | Size | Description |
|---|---|---|
| 0x00 | 4 | Read FIFO |
| 0x04 | 4 | Write FIFO |
| 0x08 | 4 | Configuration |
| 0x0C | 4 | Interrupt control? |
| 0x10 | 4 | Start transfer (write 0b1), cancel transfer(write 0b0), transfer busy (reads bit0 = 0)? |
| 0x14 | 4 | ?? |
| 0x18 | 4 | Start transfer (bit 0 or 1), transfer direction (bit 0 or 1)? |
| 0x24 | 4 | Flags? |
| 0x28 | 4 | Number of available bytes to read from the FIFO |
| 0x2C | 4 | Number of pending bytes in the write the FIFO (maximum = 0x7F) |