Difference between revisions of "SPI Registers"
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Line 11: | Line 11: | ||
| 0xE0A10000 | | 0xE0A10000 | ||
|- | |- | ||
− | | SceSpi2Reg (SceOled) | + | | SceSpi2Reg (SceOled, SceLcd) |
| 0xE0A20000 | | 0xE0A20000 | ||
|} | |} | ||
Line 20: | Line 20: | ||
! Offset | ! Offset | ||
! Size | ! Size | ||
+ | ! Name | ||
! Description | ! Description | ||
+ | |- | ||
+ | | 0x00 | ||
+ | | 4 | ||
+ | | SPI_RXFIFO | ||
+ | | Read FIFO | ||
|- | |- | ||
| 0x04 | | 0x04 | ||
| 4 | | 4 | ||
− | | FIFO | + | | SPI_TXFIFO |
+ | | Write FIFO | ||
+ | |- | ||
+ | | 0x08 | ||
+ | | 4 | ||
+ | | SPI_CTL | ||
+ | | Configuration | ||
+ | |- | ||
+ | | 0x0C | ||
+ | | 4 | ||
+ | | SPI_INTCTL | ||
+ | | Interrupt control? | ||
|- | |- | ||
| 0x10 | | 0x10 | ||
| 4 | | 4 | ||
+ | | SPI_STATUS | ||
| Start transfer (write 0b1), cancel transfer(write 0b0), transfer busy (reads bit0 = 0)? | | Start transfer (write 0b1), cancel transfer(write 0b0), transfer busy (reads bit0 = 0)? | ||
+ | |- | ||
+ | | 0x14 | ||
+ | | 4 | ||
+ | | SPI_DMACTL | ||
+ | | ?? | ||
|- | |- | ||
| 0x18 | | 0x18 | ||
| 4 | | 4 | ||
+ | | ?? | ||
| Start transfer (bit 0 or 1), transfer direction (bit 0 or 1)? | | Start transfer (bit 0 or 1), transfer direction (bit 0 or 1)? | ||
+ | |- | ||
+ | | 0x20 | ||
+ | | 4 | ||
+ | | ?? | ||
+ | | | ||
|- | |- | ||
| 0x24 | | 0x24 | ||
| 4 | | 4 | ||
− | | | + | | SPI_INT_STATUS |
+ | | Interrupt status/clear. Bit[9] = RX FIFO not empty interrupt. | ||
+ | |- | ||
+ | | 0x28 | ||
+ | | 4 | ||
+ | | SPI_RXFIFO_STATUS | ||
+ | | Number of available bytes to read from the RX FIFO | ||
|- | |- | ||
| 0x2C | | 0x2C | ||
| 4 | | 4 | ||
− | | | + | | SPI_TXFIFO_STATUS |
+ | | Number of pending bytes in the write the TX FIFO (maximum = 0x7F) | ||
|} | |} | ||
+ | |||
+ | == Notes == | ||
+ | Registers seem to be very similar to https://github.com/torvalds/linux/blob/master/drivers/spi/spi-sun4i.c |
Latest revision as of 13:56, 29 May 2021
MMIO Interfaces
Name | Physical address |
---|---|
SceSpi0Reg (SceSyscon) | 0xE0A00000 |
SceSpi1Reg (SceMotionDev) | 0xE0A10000 |
SceSpi2Reg (SceOled, SceLcd) | 0xE0A20000 |
Registers
Offset | Size | Name | Description |
---|---|---|---|
0x00 | 4 | SPI_RXFIFO | Read FIFO |
0x04 | 4 | SPI_TXFIFO | Write FIFO |
0x08 | 4 | SPI_CTL | Configuration |
0x0C | 4 | SPI_INTCTL | Interrupt control? |
0x10 | 4 | SPI_STATUS | Start transfer (write 0b1), cancel transfer(write 0b0), transfer busy (reads bit0 = 0)? |
0x14 | 4 | SPI_DMACTL | ?? |
0x18 | 4 | ?? | Start transfer (bit 0 or 1), transfer direction (bit 0 or 1)? |
0x20 | 4 | ?? | |
0x24 | 4 | SPI_INT_STATUS | Interrupt status/clear. Bit[9] = RX FIFO not empty interrupt. |
0x28 | 4 | SPI_RXFIFO_STATUS | Number of available bytes to read from the RX FIFO |
0x2C | 4 | SPI_TXFIFO_STATUS | Number of pending bytes in the write the TX FIFO (maximum = 0x7F) |
Notes
Registers seem to be very similar to https://github.com/torvalds/linux/blob/master/drivers/spi/spi-sun4i.c