Difference between revisions of "SPI Registers"
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| Line 20: | Line 20: | ||
! Offset | ! Offset | ||
! Size | ! Size | ||
| + | ! Name | ||
! Description | ! Description | ||
|- | |- | ||
| 0x00 | | 0x00 | ||
| 4 | | 4 | ||
| + | | SPI_RXDATA | ||
| Read FIFO | | Read FIFO | ||
|- | |- | ||
| 0x04 | | 0x04 | ||
| 4 | | 4 | ||
| + | | SPI_TXDATA | ||
| Write FIFO | | Write FIFO | ||
|- | |- | ||
| 0x08 | | 0x08 | ||
| 4 | | 4 | ||
| + | | SPI_CTL | ||
| Configuration | | Configuration | ||
|- | |- | ||
| 0x0C | | 0x0C | ||
| 4 | | 4 | ||
| + | | SPI_INTCTL | ||
| Interrupt control? | | Interrupt control? | ||
|- | |- | ||
| 0x10 | | 0x10 | ||
| 4 | | 4 | ||
| + | | SPI_ST | ||
| Start transfer (write 0b1), cancel transfer(write 0b0), transfer busy (reads bit0 = 0)? | | Start transfer (write 0b1), cancel transfer(write 0b0), transfer busy (reads bit0 = 0)? | ||
|- | |- | ||
| 0x14 | | 0x14 | ||
| 4 | | 4 | ||
| + | | SPI_DMACTL | ||
| ?? | | ?? | ||
|- | |- | ||
| 0x18 | | 0x18 | ||
| 4 | | 4 | ||
| + | | SPI_WAIT | ||
| Start transfer (bit 0 or 1), transfer direction (bit 0 or 1)? | | Start transfer (bit 0 or 1), transfer direction (bit 0 or 1)? | ||
|- | |- | ||
| 0x24 | | 0x24 | ||
| 4 | | 4 | ||
| + | | SPI_TC | ||
| Flags? | | Flags? | ||
|- | |- | ||
| 0x28 | | 0x28 | ||
| 4 | | 4 | ||
| + | | SPI_FIFO_STA | ||
| Number of available bytes to read from the FIFO | | Number of available bytes to read from the FIFO | ||
|- | |- | ||
| 0x2C | | 0x2C | ||
| 4 | | 4 | ||
| + | | ?? | ||
| Number of pending bytes in the write the FIFO (maximum = 0x7F) | | Number of pending bytes in the write the FIFO (maximum = 0x7F) | ||
|} | |} | ||
Revision as of 17:40, 16 January 2021
MMIO Interfaces
| Name | Physical address |
|---|---|
| SceSpi0Reg (SceSyscon) | 0xE0A00000 |
| SceSpi1Reg (SceMotionDev) | 0xE0A10000 |
| SceSpi2Reg (SceOled, SceLcd) | 0xE0A20000 |
Registers
| Offset | Size | Name | Description |
|---|---|---|---|
| 0x00 | 4 | SPI_RXDATA | Read FIFO |
| 0x04 | 4 | SPI_TXDATA | Write FIFO |
| 0x08 | 4 | SPI_CTL | Configuration |
| 0x0C | 4 | SPI_INTCTL | Interrupt control? |
| 0x10 | 4 | SPI_ST | Start transfer (write 0b1), cancel transfer(write 0b0), transfer busy (reads bit0 = 0)? |
| 0x14 | 4 | SPI_DMACTL | ?? |
| 0x18 | 4 | SPI_WAIT | Start transfer (bit 0 or 1), transfer direction (bit 0 or 1)? |
| 0x24 | 4 | SPI_TC | Flags? |
| 0x28 | 4 | SPI_FIFO_STA | Number of available bytes to read from the FIFO |
| 0x2C | 4 | ?? | Number of pending bytes in the write the FIFO (maximum = 0x7F) |
Notes
Registers seem to be very similar to https://github.com/torvalds/linux/blob/master/drivers/spi/spi-sun4i.c