SPI Registers

From Vita Development Wiki
Revision as of 18:19, 11 November 2019 by Xerpi (talk | contribs)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to navigation Jump to search

MMIO Interfaces

Name Physical address
SceSpi0Reg (SceSyscon) 0xE0A00000
SceSpi1Reg (SceMotionDev) 0xE0A10000
SceSpi2Reg (SceOled, SceLcd) 0xE0A20000


Offset Size Description
0x00 4 Read FIFO
0x04 4 Write FIFO
0x08 4 Configuration
0x0C 4 Interrupt control?
0x10 4 Start transfer (write 0b1), cancel transfer(write 0b0), transfer busy (reads bit0 = 0)?
0x14 4 ??
0x18 4 Start transfer (bit 0 or 1), transfer direction (bit 0 or 1)?
0x24 4 Flags?
0x28 4 Number of available bytes to read from the FIFO
0x2C 4 Number of pending bytes in the write the FIFO (maximum = 0x7F)