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SceCompatMailbox
| Address
|
Size
|
| 0xE5070000
|
0x1000
|
Registers
| Offset
|
Size
|
Comments
|
| 0x00 + 4 * ID
|
4
|
Raise MIPS Compat interrupt ID. Write all ones. Interrupts will become visible at 0xBC300030 on MIPS side
|
| 0x80 + 4 * ID
|
4
|
Enable raising MIPS Compat interrupt ID. Write all ones
|
Interrupt raising sequence
To raise "Compat" interrupt ID to the MIPS processor, the following sequence is used:
// Write data to shared address
shared->foo = bar;
// Trigger interrupt
dsb(0xf);
*(u32 *)(0xE5070000 + ID * 4 + 0x80) = 0xffffffff;
dsb(0xf);
*(u32 *)(0xE5070000 + ID * 4) = 0xffffffff;
dsb(0xf);