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Physical Memory (view source)

Revision as of 09:38, 12 October 2021

1,479 bytes added ,  09:38, 12 October 2021
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Line 11: Line 11:  
| 0x00007FFF
 
| 0x00007FFF
 
| 0x8000
 
| 0x8000
−
| NS/S
+
| S
−
| Alias of <code>0x1F000000</code>, ScePower scratch buffer
+
| ARM Boot. Alias of <code>0x1F000000</code>, ScePower scratch buffer
 
|-
 
|-
 
| 0x00040000
 
| 0x00040000
−
| 0x0004AFFF
+
| 0x0005FFFF
−
| 0xB000
+
| 0x20000
 +
| S
 +
| MeP boot. Mirror of 0x00800000.
 +
|-
 +
| 0x00300000
 +
| 0x0030FFFF
 +
| 0x10000
 +
| S
 +
| cmep icache
 +
|-
 +
| 0x00310000
 +
| 0x0031FFFF
 +
| 0x10000
 +
| S
 +
| cmep icache tag
 +
|-
 +
| 0x00320000
 +
| 0x0032FFFF
 +
| 0x10000
 
| S
 
| S
−
| Mirror of 0x00800000.
+
| cmep dcache
 
|-
 
|-
−
| 0x0004B000
+
| 0x00330000
−
| 0x0005FFFF
+
| 0x0033FFFF
−
| 0x15000
+
| 0x10000
 +
| S
 +
| cmep dcache tag
 +
|-
 +
| 0x004B0000
 +
| 0x005FFFFF
 +
| 0x150000
 
| S
 
| S
−
| Mirror of 0x0080B000.
+
| Reverved for Venezia
 
|-
 
|-
−
| 0x00800000
+
| 0x00600000
−
| 0x0080AFFF
+
| 0x007FFFFF
−
| 0xB000
+
| 0x200000
 
| S
 
| S
−
| [[Secure_Kernel|secure kernel]]
+
| Reserved for MeP
 
|-
 
|-
−
| 0x0080B000
+
| 0x00800000
 
| 0x0081FFFF
 
| 0x0081FFFF
−
| 0x15000
+
| 0x20000
 
| S
 
| S
−
| [[Sm_modules|sm location]]
+
| cMeP 128KiB SRAM. [[Secure_Kernel|secure kernel]], [[Sm_modules|sm location]]. Mirror of SPAD128K ?
 
|-
 
|-
 
| 0x1A000000
 
| 0x1A000000
Line 42: Line 66:  
| 0x2000
 
| 0x2000
 
| NS/S
 
| NS/S
−
| SceInterruptControllerReg / ScePeriphReg, [[Interrupts]] (<code>PERIPHBASE</code>)
+
| ARM, SceInterruptControllerReg / ScePeriphReg, [[Interrupts]] (<code>PERIPHBASE</code>)
 
|-
 
|-
 
| 0x1A002000
 
| 0x1A002000
Line 48: Line 72:  
| 0x1000
 
| 0x1000
 
| NS/S
 
| NS/S
−
| ScePl310Reg / SceL2CacheReg, [[L2 Cache Controller]]
+
| ARM. ScePl310Reg / SceL2CacheReg, [[L2 Cache Controller]]
 
|-
 
|-
 
| 0x1C000000
 
| 0x1C000000
Line 54: Line 78:  
| 0x200000
 
| 0x200000
 
| NS/S
 
| NS/S
−
| SceDisplay / SceCameraSRAM (only 960x544 mapped)
+
| Tachyon-eDRAM. SceDisplay / SceCamera SRAM (only 960x544 pixels * 4 bytes = 0x1FE000 bytes mapped)
 
|-
 
|-
 
| 0x1F000000
 
| 0x1F000000
Line 60: Line 84:  
| 0x8000
 
| 0x8000
 
| NS/S
 
| NS/S
−
| ScePowerScratchPad32KiB
+
| SPAD32K. ScePowerScratchPad32KiB
 
|-
 
|-
 
| 0x1F840000
 
| 0x1F840000
Line 66: Line 90:  
| 0x20000
 
| 0x20000
 
| NS/S
 
| NS/S
−
| [[Venezia|SceVeneziaSpram]] - Stores Secure Kernel on boot
+
| SPAD128K. [[Venezia|SceVeneziaSpram]]. Stores Secure Kernel on boot.
 
|-
 
|-
 
| 0x20000000
 
| 0x20000000
Line 72: Line 96:  
| 0x8000000
 
| 0x8000000
 
| NS
 
| NS
−
| [[VRAM]]
+
| [[VRAM]]. Graphics bar
 +
|-
 +
| 0x30000000
 +
| ?
 +
| ?
 +
| S
 +
| Unknown. Used by [[second_loader]]
 
|-
 
|-
 
| 0x40000000
 
| 0x40000000
Line 78: Line 108:  
| 0x200000
 
| 0x200000
 
| S
 
| S
−
| Secure [[DRAM]] (extra 1 Mega before FW 3.52)
+
| [[#Secure DRAM|Secure DRAM]] (extra 1 MB before FW 3.52)
 
|-
 
|-
 
| 0x40200000
 
| 0x40200000
Line 90: Line 120:  
| 0x20000000
 
| 0x20000000
 
| NS/S
 
| NS/S
−
| [[#Non-secure Shared DRAM|Shared DRAM]] DevKit additional 512MiB
+
| [[#Non-secure Shared DRAM|Shared DRAM]] DevKit additional 512MiB. LDDR2TOP.
 
|-
 
|-
 
| 0x80000000
 
| 0x80000000
 +
| 0x9FFFFFFF
 +
| 0x20000000
 +
| NS/S
 +
| [[#Non-secure Shared DRAM|Shared DRAM]] DevKit additional 512MiB. LDDR2SUB.
 +
|-
 +
| 0xA0000000
 
| 0xBFFFFFFF
 
| 0xBFFFFFFF
−
| 0x40000000
+
| 0x20000000
 +
| NS/S
 +
| LDDR2SUB. But seems not enabled.
 +
|-
 +
| 0xC0000000
 +
| 0xDFFFFFFF
 +
| 0x20000000
 
| NS/S
 
| NS/S
−
| LDDR2 sub
+
| Reserved for Venezia. Maybe unused.
 
|-
 
|-
 
| 0xE0000000
 
| 0xE0000000
−
| ?       
+
| 0xE00FFFFF
−
| ?       
+
| 0x100000
 
| S
 
| S
−
| [[#F00D Processor|F00D Processor]]
+
| Control Register. [[#cmep|cmep]]
 
|-
 
|-
 
| 0xE0100000
 
| 0xE0100000
Line 468: Line 510:  
| 0x1000
 
| 0x1000
 
| S
 
| S
−
| Cortex A9 Debug ROM Table
+
| ARM Cortex-A9 Debug ROM Table
 
|-
 
|-
 
| 0xE3310000
 
| 0xE3310000
Line 570: Line 612:  
| 0x4000
 
| 0x4000
 
| NS
 
| NS
−
| SceIntrmgrVfpIntRegs
+
| ARM-VFP. SceIntrmgrVfpIntRegs
 
|-
 
|-
 
| 0xE4020000
 
| 0xE4020000
Line 576: Line 618:  
| 0x1000
 
| 0x1000
 
| NS
 
| NS
−
| SceUsbdEhci
+
| USB2_OHCI. SceUsbdEhci
 
|-
 
|-
 
| 0xE40B0000
 
| 0xE40B0000
Line 618: Line 660:  
| 0x1000
 
| 0x1000
 
| NS
 
| NS
−
| SceIftu0RegA (OLED FB)
+
| [[IFTU_Registers|SceIftu0RegA]] (OLED FB)
 
|-
 
|-
 
| 0xE5021000
 
| 0xE5021000
Line 624: Line 666:  
| 0x1000
 
| 0x1000
 
| NS
 
| NS
−
| SceIftu0RegB
+
| [[IFTU_Registers|SceIftu0RegB]]
 
|-
 
|-
 
| 0xE5022000
 
| 0xE5022000
Line 630: Line 672:  
| 0x1000
 
| 0x1000
 
| NS
 
| NS
−
| SceIftuc0Reg
+
| [[IFTU_Registers|SceIftuc0Reg]]
 
|-
 
|-
 
| 0xE5030000
 
| 0xE5030000
Line 636: Line 678:  
| 0x1000
 
| 0x1000
 
| NS
 
| NS
−
| SceIftu1RegA (HDMI FB)
+
| [[IFTU_Registers|SceIftu1RegA]] (HDMI FB)
 
|-
 
|-
 
| 0xE5031000
 
| 0xE5031000
Line 642: Line 684:  
| 0x1000
 
| 0x1000
 
| NS
 
| NS
−
| SceIftu1RegB
+
| [[IFTU_Registers|SceIftu1RegB]]
 
|-
 
|-
 
| 0xE5032000
 
| 0xE5032000
Line 648: Line 690:  
| 0x1000
 
| 0x1000
 
| NS
 
| NS
−
| SceIftuc1Reg
+
| [[IFTU_Registers|SceIftuc1Reg]]
 
|-
 
|-
 
| 0xE5040000
 
| 0xE5040000
Line 654: Line 696:  
| 0x1000
 
| 0x1000
 
| NS
 
| NS
−
| SceIftu2Reg
+
| [[IFTU_Registers|SceIftu2Reg]]
 
|-
 
|-
 
| 0xE5050000
 
| 0xE5050000
Line 691: Line 733:  
| NS
 
| NS
 
| ScePfmReg / SceDeci4pDtracepPaReg
 
| ScePfmReg / SceDeci4pDtracepPaReg
 +
|-
 +
| 0xE5800000
 +
| 0xE580FFFF
 +
| 0x10000
 +
| NS
 +
| SceSDbgSdio0
 +
|-
 +
| 0xE5810000
 +
| 0xE581FFFF
 +
| 0x10000
 +
| NS
 +
| SceDbgSdio1
 
|-
 
|-
 
| 0xE5880000
 
| 0xE5880000
Line 708: Line 762:  
| 0x2000
 
| 0x2000
 
| S
 
| S
−
| SceSonyRegbus
+
| SceSonyRegbus. GPU Control
 
|-
 
|-
 
| 0xE8100000
 
| 0xE8100000
Line 739: Line 793:  
| ?
 
| ?
 
| Mapped by SKBL
 
| Mapped by SKBL
 +
|-
 +
| 0xEC060000
 +
| ?
 +
| ?
 +
| ?
 +
| Mapped by SKBL. Maybe related to cmep reset.
 
|-
 
|-
 
| 0xED000000
 
| 0xED000000
Line 751: Line 811:  
| ?
 
| ?
 
| Mapped by SKBL
 
| Mapped by SKBL
 +
|-
 +
| 0xF0000000
 +
| ?
 +
| ?
 +
| ?
 +
| Reserved for Venezia
 
|}
 
|}
    
== Secure DRAM ==
 
== Secure DRAM ==
 +
 +
=== FW 3.60 Secure DRAM ===
    
{| class='wikitable'
 
{| class='wikitable'
Line 764: Line 832:  
| 0x400000BF
 
| 0x400000BF
 
| 0xC0
 
| 0xC0
−
| some Reset Vector, like 0x51000000
+
| SKBL Reset Vector
 
|-
 
|-
 
| 0x40000500
 
| 0x40000500
 
| 0x400099FF
 
| 0x400099FF
 
| 0x9500
 
| 0x9500
−
| kprx_auth_sm.self raw data (encrypted)
+
| kprx_auth_sm.self
 
|-
 
|-
 
| 0x40009B00
 
| 0x40009B00
 
| 0x4000A27F
 
| 0x4000A27F
 
| 0x780
 
| 0x780
−
| some self raw data (encrypted) ?rvk?
+
| prog_rvk.srvk
 
|-
 
|-
 
| 0x4001FD00
 
| 0x4001FD00
 
| 0x4001FEFF
 
| 0x4001FEFF
 
| 0x100
 
| 0x100
−
| KblParam but Magic is not set
+
| SceKblParam with magic not set
 
|-
 
|-
 
| 0x40020000
 
| 0x40020000
 
| 0x400570C7
 
| 0x400570C7
 
| 0x370C8
 
| 0x370C8
−
| secure kernel bootloader text segment
+
| SKBL segment 0
 
|-
 
|-
 
| 0x40057100
 
| 0x40057100
−
| ?
+
| 0x400571DF
−
| ?
+
| 0xE0
−
| secure kernel bootloader data segment
+
| SKBL segment 1
 
|-
 
|-
 
| 0x40073570
 
| 0x40073570
Line 799: Line 867:  
== Non-secure Shared DRAM ==
 
== Non-secure Shared DRAM ==
   −
This are is used by both Secure and Non-Secure Kernel Boot Loaders, and by Secure kernel modules.
+
This region is used by both Secure and Non-Secure Kernel Boot Loaders, and by Secure kernel modules.
    
{| class='wikitable'
 
{| class='wikitable'
Line 815: Line 883:  
| 0x50FFFFFF
 
| 0x50FFFFFF
 
| 0x1000000
 
| 0x1000000
−
| ARZL compressed NSKBL
+
| ARZL compressed NSKBL. Comes from one of kernel_boot_loader.self segments.
 
|-
 
|-
−
| 0x510000C0
+
| 0x51000000
 
| 0x51FFFFFF
 
| 0x51FFFFFF
 
| 0x1000000
 
| 0x1000000
−
| uncompressed [[NSKBL]]
+
| SceBootKernelImage. uncompressed [[NSKBL]]. Comes from ARZL compressed NSKBL.
 
|-
 
|-
 
| 0x52000000
 
| 0x52000000
Line 826: Line 894:  
| 0xE000000
 
| 0xE000000
 
| non-secure kernel and userland modules
 
| non-secure kernel and userland modules
 +
|-
 +
| 0x60000000
 +
| 0x7FFFFFFF
 +
| 0x20000000
 +
| Devkit additional 512MiB RAM
 +
|-
 +
| 0x80000000
 +
| 0x9FFFFFFF
 +
| 0x20000000
 +
| Devkit additional 512MiB RAM for perf (Not published anywhere)
 +
|-
 +
| 0xA0000000
 +
| 0xBFFFFFFF
 +
| 0x20000000
 +
| Devkit additional 512MiB RAM for perf (Not published anywhere, Also disabled)
 
|}
 
|}
   Line 850: Line 933:     
Notes:
 
Notes:
−
*The first 0xC0 bytes of the Text segment are the reset vector.
+
* The first 0xC0 bytes of the Text segment are the reset vector.
 
* NSKBL is mapped in RWX mode so it may write itself to text segment.
 
* NSKBL is mapped in RWX mode so it may write itself to text segment.
   −
== F00D Processor ==
+
== cmep ==
   −
Each F00D device has its own physical memory area.
+
Each cmep device has its own physical memory area.
    
{| class='wikitable'
 
{| class='wikitable'
Line 868: Line 951:  
| 0xE0010000
 
| 0xE0010000
 
| 0xE001FFFF
 
| 0xE001FFFF
−
| F00D Reset
+
| cmep Reset
 
|-
 
|-
 
| 0xE0020000
 
| 0xE0020000
Xerpi
708

edits

Retrieved from "http://wiki.henkaku.xyz/vita/Special:MobileDiff/15312...16185"