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- [[Category:ARM]]3 KB (299 words) - 21:38, 1 May 2023
- [[Category:ARM]]933 bytes (91 words) - 00:22, 1 April 2024
- [[Category:ARM]]145 bytes (21 words) - 21:39, 1 May 2023
- Any device connected to the memory system, such as ARM cores, DMA controllers, LPDDR2... A module that can initiate read and write requests to the interconnect (e.g. ARM cores, DMA, ...).9 KB (1,367 words) - 17:27, 25 November 2023
- Requests ARM [[TrustZone]] using [[SMC]] 0x114. [[Category:ARM]]56 KB (6,898 words) - 22:15, 5 February 2024
- [[Category:ARM]]10 KB (983 words) - 21:01, 1 May 2023
- [[Category:ARM]]8 KB (646 words) - 20:46, 1 May 2023
- [[Category:ARM]]3 KB (334 words) - 00:04, 1 April 2024
- [[Category:ARM]]3 KB (308 words) - 21:07, 1 May 2023
- [[Category:ARM]]1 KB (171 words) - 21:19, 1 May 2023
- [[Category:ARM]]5 KB (534 words) - 16:00, 30 March 2024
- ...ler is defined in the MPCore TRM [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407i/CACCJFCJ.html]. The PERIPHBASE address (physical) is 0x1A00000 [[Category:ARM]]30 KB (3,151 words) - 05:56, 13 October 2023
- [[Category:ARM]]13 KB (1,337 words) - 11:44, 7 June 2023
- [[Category:ARM]]2 KB (160 words) - 21:43, 1 May 2023
- ....self does not itself run on cmep but only contains encrypted segments for ARM to run. Unless indicated otherwise, all processes are encrypted and require === ARM Secure Kernel ===6 KB (1,004 words) - 08:27, 4 August 2023
- @param[in] arm_opcode - Opcode of the ARM instruction that triggered breakpoint (reversed endianness) @param[in] arm_opcode - Opcode of the ARM instruction that triggered breakpoint (reversed endianness)5 KB (642 words) - 13:11, 9 June 2023
- [[Category:ARM]]965 bytes (112 words) - 21:06, 1 May 2023
- [[Category:ARM]]127 bytes (14 words) - 20:56, 1 May 2023
- [[Category:ARM]]6 KB (725 words) - 18:04, 11 August 2023
- [[Category:ARM]]4 KB (491 words) - 20:38, 1 May 2023