UART Registers
Revision as of 07:37, 14 June 2017 by Xerpi (talk | contribs) (Created page with "== MMIO Interfaces == {| class='wikitable' |- ! Name ! Physical address ! Size |- | SceUartReg | 0xE2030000 | 0x70000 |- | SceUartClkgenReg | 0xE3105000 | 0x10...")
MMIO Interfaces
| Name | Physical address | Size |
|---|---|---|
| SceUartReg | 0xE2030000 | 0x70000 |
| SceUartClkgenReg | 0xE3105000 | 0x1000 |
SceUartReg registers
| Offset | Size | Description |
|---|---|---|
| 0x68 | 4 | Read FIFO data available |
| 0x78 | 4 | Read FIFO |
Read FIFO data available
| Bit(s) | Description |
|---|---|
| 0-5 | Number of words available to read |
| 6-31 | Unused |