DSI Registers: Difference between revisions
Jump to navigation
Jump to search
No edit summary |
No edit summary |
||
(27 intermediate revisions by 2 users not shown) | |||
Line 15: | Line 15: | ||
{| class='wikitable' | {| class='wikitable' | ||
|- | |- | ||
! Engine | |||
! Offset | ! Offset | ||
! Size | ! Size | ||
! Description | ! Description | ||
|- | |- | ||
| rowspan=20 style="text-align: center;" | RGB output | |||
| 0x004 | | 0x004 | ||
| 4 | | 4 | ||
| bits 1:0: Video mode (0 = Progressive, 0b11 = Interlaced) | | bits[1:0]: Video mode (0 = Progressive, 0b11 = Interlaced) | ||
|- | |||
| 0x008 | |||
| 4 | |||
| bits[31:0]: <code>(htotal * clocks_per_pixel) >> 1</code> | |||
|- | |- | ||
| 0x00C | | 0x00C | ||
| 4 | | 4 | ||
| | | bits[28:16]: <code>vtotal</code>, bits[12:0]: <code>(vtotal + 1) >> 1</code> | ||
|- | |||
| 0x010 | |||
| 4 | |||
| bits[31:0]: <code>0x10001</code> | |||
|- | |- | ||
| 0x014 | | 0x014 | ||
| 4 | | 4 | ||
| | | bits[31:16]: <code>((HSW + HBP) * clocks_per_pixel) >> 1</code>, bits[15:0]: <code>(((HSW + HBP + hact) * clocks_per_pixel) >> 1) + 1</code> | ||
|- | |||
| 0x01C | |||
| 4 | |||
| bits[28:16]: <code>VSW + VBP - 1</code>, bits[12:0]: <code>((vtotal + 1) >> 1) - VFP</code> | |||
|- | |||
| 0x020 | |||
| 4 | |||
| bits[28:16]: <code>VSW + VBP + ((vtotal - 1) >> 1)</code>, bits[12:0]: <code>vtotal - VFP + 1</code> | |||
|- | |||
| 0x024 | |||
| 4 | |||
| bits[31:16]: <code>(HSW * clocks_per_pixel) >> 1</code>, bit[0]: <code>1</code> | |||
|- | |||
| 0x02C | |||
| 4 | |||
| bits[31:0]: <code>0x10001</code> | |||
|- | |- | ||
| 0x030 | | 0x030 | ||
| 4 | | 4 | ||
| bits[31:16] = | | bits[28:16]: <code>VSW</code>, bits[15:0]: <code>(htotal * clocks_per_pixel) >> 1</code> | ||
|- | |||
| 0x034 | |||
| 4 | |||
| bits[28:16]: <code>(vtotal + 1) >> 1</code>, bits[15:0]: <code>((htotal * clocks_per_pixel) >> 2) + 1</code> | |||
|- | |||
| 0x038 | |||
| 4 | |||
| bits[28:16]: <code>VSW + ((vtotal + 1) >> 1)</code>, bits[15:0]: <code>(htotal * clocks_per_pixel) >> 2</code> | |||
|- | |||
| 0x03C | |||
| 4 | |||
| bits[31:0]: <code>1</code> | |||
|- | |||
| 0x040 | |||
| 4 | |||
| bits[28:16]: <code>((vtotal + 1) >> 1) + (VSW + VBP) - 8</code>, bits[15:0]: <code>(VSW + VBP) - 8</code> | |||
|- | |||
| 0x048 | |||
| 4 | |||
| bits[7:0]: pending interrupts or some counter ?? | |||
|- | |||
| 0x04C | |||
| 4 | |||
| bits[31:16]: current <code>Vcount</code>, bits[15:0]: ?? | |||
|- | |||
| 0x050 | |||
| 4 | |||
| Interrupts ack/clear (read = triggered interrupts, write = clear interrupt) | |||
|- | |- | ||
| 0x054 | | 0x054 | ||
| 4 | | 4 | ||
| Interrupt | | Interrupt enable mask (bit 1 = some interrupt) | ||
|- | |- | ||
| 0x05C | |||
| 4 | |||
| | |||
{| class="wikitable" | |||
! Progressive !! Interlaced | |||
|- | |||
| 0x10001 || bits[28:16]: <code>(vtotal + 1) >> 1</code>, bits[15:0]: <code>1</code> | |||
|} | |||
|- | |||
| 0x060 | |||
| 4 | |||
| | |||
{| class="wikitable" | |||
! Progressive !! Interlaced | |||
|- | |||
| bits[28:16]: <code>VSW + VBP</code>, bits[15:0]: <code>1</code> || bits[28:16]: <code>VSW + VBP + ((vtotal - 1) >> 1)</code>, bits[15:0]: <code>1</code> | |||
|} | |||
|- | |||
| rowspan=3 style="text-align: center;" | RGB-to-DSI PHY Rx | |||
| 0x410 | |||
| 4 | |||
| DSI_STATUS. DSI Command read FIFO status (bit 5 = Read FIFO *not* empty) | |||
|- | |||
| 0x414 | |||
| 4 | |||
| DSI_INT. Some sort of status. Ready/busy? | |||
|- | |||
| 0x430 | |||
| 4 | |||
| DSICMD_RXFIFO. DSI Command read FIFO | |||
|- | |||
| rowspan=6 style="text-align: center;" | RGB-to-DSI PHY Tx | |||
| 0x500 | | 0x500 | ||
| 4 | | 4 | ||
| Command FIFO. | | DSI_CONFW?. DSI Command FIFO | ||
|- | |||
| 0x504 | |||
| 4 | |||
| DSI_RESET?. DSI Command FIFO packet size (in multiples of 32b) | |||
|- | |||
| 0x508 | |||
| 4 | |||
| | |||
|- | |||
| 0x50C | |||
| 4 | |||
| DSI_INT_CLR | |||
|- | |- | ||
| 0x510 | | 0x510 | ||
| 4 | | 4 | ||
| Another command FIFO. | | Another command FIFO (used to write the packet for command reads) | ||
|- | |||
| 0x51C | |||
| 4 | |||
| Transfer control. bit[0]: Transfer direction (0 = read, 1 = write). Seems to be some kind of SPI/I2C interface | |||
|- | |||
| rowspan=21 style="text-align: center;" | Clocking | |||
| 0x804 | |||
| 4 | |||
| | |||
|- | |||
| 0x810 | |||
| 4 | |||
| | |||
|- | |||
| 0x814 | |||
| 4 | |||
| | |||
|- | |||
| 0x818 | |||
| 4 | |||
| | |||
|- | |||
| 0x81C | |||
| 4 | |||
| | |||
|- | |||
| 0x820 | |||
| 4 | |||
| | |||
|- | |||
| 0x824 | |||
| 4 | |||
| | |||
|- | |||
| 0x828 | |||
| 4 | |||
| | |||
|- | |||
| 0x82C | |||
| 4 | |||
| | |||
|- | |||
| 0x830 | |||
| 4 | |||
| | |||
|- | |||
| 0x834 | |||
| 4 | |||
| | |||
|- | |- | ||
| 0x838 | | 0x838 | ||
| 4 | | 4 | ||
| DSI auto clock configuration (only HS clock) | | DSI auto clock configuration (1 = only HS clock, 0 = auto gate when data in LP) | ||
|- | |||
| 0x83C | |||
| 4 | |||
| | |||
|- | |||
| 0x900 | |||
| 4 | |||
| | |||
|- | |||
| 0x904 | |||
| 4 | |||
| | |||
|- | |||
| 0x908 | |||
| 4 | |||
| | |||
|- | |||
| 0x90C | |||
| 4 | |||
| | |||
|- | |||
| 0x940 | |||
| 4 | |||
| | |||
|- | |||
| 0x944 | |||
| 4 | |||
| | |||
|- | |||
| 0x948 | |||
| 4 | |||
| | |||
|- | |||
| 0x94C | |||
| 4 | |||
| | |||
|} | |} |
Latest revision as of 10:27, 2 November 2019
MMIO Interfaces
Name | Physical address |
---|---|
SceDsi0Reg | 0xE5050000 |
SceDsi1Reg | 0xE5060000 |
Registers
Engine | Offset | Size | Description | |||
---|---|---|---|---|---|---|
RGB output | 0x004 | 4 | bits[1:0]: Video mode (0 = Progressive, 0b11 = Interlaced) | |||
0x008 | 4 | bits[31:0]: (htotal * clocks_per_pixel) >> 1
| ||||
0x00C | 4 | bits[28:16]: vtotal , bits[12:0]: (vtotal + 1) >> 1
| ||||
0x010 | 4 | bits[31:0]: 0x10001
| ||||
0x014 | 4 | bits[31:16]: ((HSW + HBP) * clocks_per_pixel) >> 1 , bits[15:0]: (((HSW + HBP + hact) * clocks_per_pixel) >> 1) + 1
| ||||
0x01C | 4 | bits[28:16]: VSW + VBP - 1 , bits[12:0]: ((vtotal + 1) >> 1) - VFP
| ||||
0x020 | 4 | bits[28:16]: VSW + VBP + ((vtotal - 1) >> 1) , bits[12:0]: vtotal - VFP + 1
| ||||
0x024 | 4 | bits[31:16]: (HSW * clocks_per_pixel) >> 1 , bit[0]: 1
| ||||
0x02C | 4 | bits[31:0]: 0x10001
| ||||
0x030 | 4 | bits[28:16]: VSW , bits[15:0]: (htotal * clocks_per_pixel) >> 1
| ||||
0x034 | 4 | bits[28:16]: (vtotal + 1) >> 1 , bits[15:0]: ((htotal * clocks_per_pixel) >> 2) + 1
| ||||
0x038 | 4 | bits[28:16]: VSW + ((vtotal + 1) >> 1) , bits[15:0]: (htotal * clocks_per_pixel) >> 2
| ||||
0x03C | 4 | bits[31:0]: 1
| ||||
0x040 | 4 | bits[28:16]: ((vtotal + 1) >> 1) + (VSW + VBP) - 8 , bits[15:0]: (VSW + VBP) - 8
| ||||
0x048 | 4 | bits[7:0]: pending interrupts or some counter ?? | ||||
0x04C | 4 | bits[31:16]: current Vcount , bits[15:0]: ??
| ||||
0x050 | 4 | Interrupts ack/clear (read = triggered interrupts, write = clear interrupt) | ||||
0x054 | 4 | Interrupt enable mask (bit 1 = some interrupt) | ||||
0x05C | 4 |
| ||||
0x060 | 4 |
| ||||
RGB-to-DSI PHY Rx | 0x410 | 4 | DSI_STATUS. DSI Command read FIFO status (bit 5 = Read FIFO *not* empty) | |||
0x414 | 4 | DSI_INT. Some sort of status. Ready/busy? | ||||
0x430 | 4 | DSICMD_RXFIFO. DSI Command read FIFO | ||||
RGB-to-DSI PHY Tx | 0x500 | 4 | DSI_CONFW?. DSI Command FIFO | |||
0x504 | 4 | DSI_RESET?. DSI Command FIFO packet size (in multiples of 32b) | ||||
0x508 | 4 | |||||
0x50C | 4 | DSI_INT_CLR | ||||
0x510 | 4 | Another command FIFO (used to write the packet for command reads) | ||||
0x51C | 4 | Transfer control. bit[0]: Transfer direction (0 = read, 1 = write). Seems to be some kind of SPI/I2C interface | ||||
Clocking | 0x804 | 4 | ||||
0x810 | 4 | |||||
0x814 | 4 | |||||
0x818 | 4 | |||||
0x81C | 4 | |||||
0x820 | 4 | |||||
0x824 | 4 | |||||
0x828 | 4 | |||||
0x82C | 4 | |||||
0x830 | 4 | |||||
0x834 | 4 | |||||
0x838 | 4 | DSI auto clock configuration (1 = only HS clock, 0 = auto gate when data in LP) | ||||
0x83C | 4 | |||||
0x900 | 4 | |||||
0x904 | 4 | |||||
0x908 | 4 | |||||
0x90C | 4 | |||||
0x940 | 4 | |||||
0x944 | 4 | |||||
0x948 | 4 | |||||
0x94C | 4 |