SceCompatMailbox: Difference between revisions

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(Created page with "== SceCompatMailbox == {| class='wikitable' |- ! Address ! Size |- | 0xE5070000 | 0x1000 |} == Registers == {| class='wikitable' |- ! Offset ! Size ! Comments |- | 0x00 + 4...")
 
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Line 20: Line 20:
| 0x00 + 4 * ID
| 0x00 + 4 * ID
| 4
| 4
| Enable raising MIPS Compat interrupt <code>ID</code>. Write all ones
| Raise MIPS Compat interrupt <code>ID</code>. Write all ones. Interrupts will become visible at <code>0xBC300030</code> on [[PSP_Emulator#Interrupt_manager|MIPS side]]
|-
|-
| 0x80 + 4 * ID
| 0x80 + 4 * ID
| 4
| 4
| Raise MIPS Compat interrupt <code>ID</code>. Write all ones. Visible at <code>0xBC300030</code> on [[PSP_Emulator#Interrupt_manager|MIPS side]]
| Enable raising MIPS Compat interrupt <code>ID</code>. Write all ones
|}
|}
== Interrupt raising sequence ==
To raise "Compat" interrupt <code>ID</code> to the MIPS processor, the following sequence is used:
<source lang="c">
// Write data to shared address
shared->foo = bar;
// Trigger interrupt
dsb(0xf);
*(u32 *)(0xE5070000 + ID * 4 + 0x80) = 0xffffffff;
dsb(0xf);
*(u32 *)(0xE5070000 + ID * 4) = 0xffffffff;
dsb(0xf);
</source>
[[Category:Kernel]]
[[Category:MMIO]]

Latest revision as of 20:52, 1 May 2023

SceCompatMailbox

Address Size
0xE5070000 0x1000

Registers

Offset Size Comments
0x00 + 4 * ID 4 Raise MIPS Compat interrupt ID. Write all ones. Interrupts will become visible at 0xBC300030 on MIPS side
0x80 + 4 * ID 4 Enable raising MIPS Compat interrupt ID. Write all ones

Interrupt raising sequence

To raise "Compat" interrupt ID to the MIPS processor, the following sequence is used:

// Write data to shared address
shared->foo = bar;
// Trigger interrupt
dsb(0xf);
*(u32 *)(0xE5070000 + ID * 4 + 0x80) = 0xffffffff;
dsb(0xf);
*(u32 *)(0xE5070000 + ID * 4) = 0xffffffff;
dsb(0xf);