ARM Debugger Interface: Difference between revisions

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[https://developer.arm.com/documentation/ddi0461/b/Programmers-Model/Register-summary CoreSight Trace Memory Controller]
The PS Vita has an ARM debugger interface in the form of the [https://developer.arm.com/documentation/ddi0444/a/Programmers-Model/Register-summary CoreSight System Trace Macrocell (STM)].


== ROM Table ==
== ROM Table ==
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== Additional reading ==
This section lists publications by ARM.
See [http://infocenter.arm.com/ Infocenter], for access to ARM documentation.
=== ARM publications ===
See the following documents for other relevant information:
* CoreSight System Trace Macrocell Implementation and Integration Manual (PR430-PRDC-011726)
* System Trace Macrocell Programmers' Model Architecture Specification (ARM IHI 0054)
* ARMv7-M Architecture Reference Manual (ARM DDI 0403)
* ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition (ARM DDI 0406)
* Embedded Trace Macrocell Architecture Specification (ARM IHI 0014)
* CoreSight Architecture Specification (ARM IHI 0029)
* CoreSight Components Technical Reference Manual (ARM DDI 0314)
* CoreSight Technology System Design Guide (ARM DGI 0012)
* ARM Debug Interface v5 Architecture Specification (ARM IHI 0031)
* AMBA AXI Protocol Specification (ARM IHI 0022)
* AMBA APB Protocol Specification (ARM IHI 0024)
* AMBA ATB Protocol Specification (ARM IHI 0032)
* AMBA DMA Controller DMA-330 Technical Reference Manual (ARM DDI 0424)
* RealView ICE and RealView Trace User Guide (ARM DUI 0155).
=== Other publications ===
This section lists relevant documents published by third parties:
* MIPI System Trace Protocol version 2 (STPv2).


[[Category:Devices]]
[[Category:Devices]]

Latest revision as of 04:11, 30 September 2024

The PS Vita has an ARM debugger interface in the form of the CoreSight System Trace Macrocell (STM).

ROM Table

Offset Size Component Class Part Number JEP 106 ID Revision Device Type Description
0x0 0x1000 0x1 = ROM Table 0x0 0x0 0x0 ROM Table
0x1000 0x1000 0x9 = Debug component 0x907 0x3B (ARM) 0x3 0x21 = Trace Sink, Buffer ETB (ARM CoreSight SoC-400)
0x2000 0x1000 0x9 = Debug component 0x906 0x3B (ARM) 0x3 0x14 = Debug Control, Trigger Matrix CTI (ARM CoreSight SoC-400)
0x3000 0x1000 0x9 = Debug component 0x912 0x3B (ARM) 0x4 0x11 = Trace Sink, Trace Port TPIU (ARM CoreSight SoC-400)
0x4000 0x1000 0x9 = Debug component 0x908 0x3B (ARM) 0x1 0x12 = Trace Link, Trace funnel, Router. Funnel (ARM CoreSight SoC-400)
0x5000 0x1000 0x9 = Debug component 0x913 0x3B (ARM) 0x2 0x43 = Trace Source, Bus ITM (CoreSight Design Kits)
0x100000 0x1000 0x1 = ROM Table 0x4A9 0x3B (ARM) 0x0 Cortex A9 SMP ROM Table
0x110000 0x1000 0x9 = Debug component 0xC09 0x3B (ARM) 0x0 0x15 = Debug Logic, Processor core DBG0 (Cortex A9)
0x111000 0x1000 0x9 = Debug component 0x9A0 0x3B (ARM) 0x0 0x15 = Performance Monitor, Processor PMU0 (Cortex A9)
0x112000 0x1000 0x9 = Debug component 0xC09 0x3B (ARM) 0x0 0x15 = Debug Logic, Processor core DBG1 (Cortex A9)
0x113000 0x1000 0x9 = Debug component 0x9A0 0x3B (ARM) 0x0 0x15 = Performance Monitor, Processor PMU1 (Cortex A9)
0x114000 0x1000 0x9 = Debug component 0xC09 0x3B (ARM) 0x0 0x15 = Debug Logic, Processor core DBG2 (Cortex A9)
0x115000 0x1000 0x9 = Debug component 0x9A0 0x3B (ARM) 0x0 0x15 = Performance Monitor, Processor PMU2 (Cortex A9)
0x116000 0x1000 0x9 = Debug component 0xC09 0x3B (ARM) 0x0 0x15 = Debug Logic, Processor core DBG3 (Cortex A9)
0x117000 0x1000 0x9 = Debug component 0x9A0 0x3B (ARM) 0x0 0x15 = Performance Monitor, Processor PMU3 (Cortex A9)
0x118000 0x1000 0x9 = Debug component 0x906 0x3B (ARM) 0x3 0x14 = Debug Control, Trigger Matrix CTI0 (ARM CoreSight SoC-400)
0x119000 0x1000 0x9 = Debug component 0x906 0x3B (ARM) 0x3 0x14 = Debug Control, Trigger Matrix CTI1 (ARM CoreSight SoC-400)
0x11A000 0x1000 0x9 = Debug component 0x906 0x3B (ARM) 0x3 0x14 = Debug Control, Trigger Matrix CTI2 (ARM CoreSight SoC-400)
0x11B000 0x1000 0x9 = Debug component 0x906 0x3B (ARM) 0x3 0x14 = Debug Control, Trigger Matrix CTI3 (ARM CoreSight SoC-400)
0x11C000 0x1000 0x9 = Debug component 0x950 0x3B (ARM) 0x1 0x13 = Trace Source, Processor PTM0 (CoreSight PTM-A9)
0x11D000 0x1000 0x9 = Debug component 0x950 0x3B (ARM) 0x1 0x13 = Trace Source, Processor PTM1 (CoreSight PTM-A9)
0x11E000 0x1000 0x9 = Debug component 0x950 0x3B (ARM) 0x1 0x13 = Trace Source, Processor PTM2 (CoreSight PTM-A9)
0x11F000 0x1000 0x9 = Debug component 0x950 0x3B (ARM) 0x1 0x13 = Trace Source, Processor PTM3 (CoreSight PTM-A9)

Additional reading

This section lists publications by ARM.

See Infocenter, for access to ARM documentation.

ARM publications

See the following documents for other relevant information:

  • CoreSight System Trace Macrocell Implementation and Integration Manual (PR430-PRDC-011726)
  • System Trace Macrocell Programmers' Model Architecture Specification (ARM IHI 0054)
  • ARMv7-M Architecture Reference Manual (ARM DDI 0403)
  • ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition (ARM DDI 0406)
  • Embedded Trace Macrocell Architecture Specification (ARM IHI 0014)
  • CoreSight Architecture Specification (ARM IHI 0029)
  • CoreSight Components Technical Reference Manual (ARM DDI 0314)
  • CoreSight Technology System Design Guide (ARM DGI 0012)
  • ARM Debug Interface v5 Architecture Specification (ARM IHI 0031)
  • AMBA AXI Protocol Specification (ARM IHI 0022)
  • AMBA APB Protocol Specification (ARM IHI 0024)
  • AMBA ATB Protocol Specification (ARM IHI 0032)
  • AMBA DMA Controller DMA-330 Technical Reference Manual (ARM DDI 0424)
  • RealView ICE and RealView Trace User Guide (ARM DUI 0155).

Other publications

This section lists relevant documents published by third parties:

  • MIPI System Trace Protocol version 2 (STPv2).
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