SPI Registers: Difference between revisions
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(Created page with "== MMIO Interfaces == {| class='wikitable' |- ! Name ! Physical address |- | SceSpi0Reg (SceSyscon) | 0xE0A00000 |- | SceSpi1Reg (SceMotionDev) | 0xE0A10000 |- | SceSpi2Reg (S...") |
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| Line 25: | Line 25: | ||
| 4 | | 4 | ||
| FIFO | | FIFO | ||
|- | |||
| 0x10 | |||
| 4 | |||
| Start transfer (write a 0), transfer finished (reads bit0 = 0)? | |||
|- | |- | ||
| 0x2C | | 0x2C | ||
Revision as of 10:08, 14 February 2017
MMIO Interfaces
| Name | Physical address |
|---|---|
| SceSpi0Reg (SceSyscon) | 0xE0A00000 |
| SceSpi1Reg (SceMotionDev) | 0xE0A10000 |
| SceSpi2Reg (SceOled) | 0xE0A20000 |
Registers
| Offset | Size | Description |
|---|---|---|
| 0x04 | 4 | FIFO |
| 0x10 | 4 | Start transfer (write a 0), transfer finished (reads bit0 = 0)? |
| 0x2C | 4 | Transfer length? |