SPI Registers: Difference between revisions

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Line 28: Line 28:
| 0x10
| 0x10
| 4
| 4
| Start transfer (write a 0), transfer finished (reads bit0 = 0)?
| Start transfer (write 0b1), cancel transfer(write 0b0), transfer busy (reads bit0 = 0)?
|-
| 0x18
| 4
| Start transfer (bit 0 or 1), transfer direction (bit 0 or 1)?
|-
|-
| 0x2C
| 0x2C

Revision as of 10:30, 14 February 2017

MMIO Interfaces

Name Physical address
SceSpi0Reg (SceSyscon) 0xE0A00000
SceSpi1Reg (SceMotionDev) 0xE0A10000
SceSpi2Reg (SceOled) 0xE0A20000

Registers

Offset Size Description
0x04 4 FIFO
0x10 4 Start transfer (write 0b1), cancel transfer(write 0b0), transfer busy (reads bit0 = 0)?
0x18 4 Start transfer (bit 0 or 1), transfer direction (bit 0 or 1)?
0x2C 4 Transfer length?