SGX543: Difference between revisions

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Revision as of 22:55, 16 February 2018

Instruction set

General Info

It looks like instructions are 8 bytes long. Roughly speaking - first 4 bytes contain opcode and addressing mode. Second 4 bytes contain operands encoding.

Bit encoding used in this reference:

value meaning
0 bit clear
1 bit set
x dont care
? unknown
see reference

Predicates

Not sure about predicates yet, but they are used to mask execution of certain instructions.

Notation is the following: 

<predicate> <instruction>

For example: 

!p0 mad.f32

To reduce amount of examples - they are not listed with predicates.

It is assumed that all predicates are applicable to all instructions in the group unless opposite is indicated.

Operands

Currently - only known form of operands is registers.

Instructions may have up to four operands specified.

In this documentation they will be encoded as: 

<op0> <op1> <op2> <op3>

Registers

  • pa - primary attribute register. 32 bit long.
  • sa - secondary attribute register. 32 bit long.
  • o - output register. 32 bit long.
  • r - temporary register. 32 bit long.
  • i - internal register. 128 bit long.

Register Selector RS2

This encoding uses 2 bits to encode register type.

selector is encoded as:

1 0 meaning
0 0 r
0 1 o
1 0 pa
1 1 sa

Note that internal registers are not encoded - they are reserved in Register R6

Register Selector Indexable RSI2

This encoding uses 2 bits to encode register type.

selector is encoded as:

1 0 meaning
0 0 r
0 1 o
1 0 pa
1 1 index<N> mode

When index<N> mode is used - there has to be another field that encodes index expression with Register Index Offset RIO6

The way that index expression is buit: 

<reg>[index1 * 2 + <offset>]

Example: 

r[index1 * 2 + 8]

Register R6

This encoding uses 6 bits to encode register index.

register is encoded as:

5 4 3 2 1 0 index
0 0 0 0 0 0 0
0 0 0 0 0 1 2
... ... ... ... ... ...
1 1 1 0 1 0 116
1 1 1 0 1 1 118
1 1 1 1 0 0 i0 (reserved)
1 1 1 1 0 1 i1 (reserved)
1 1 1 1 1 0 i2 (reserved)
1 1 1 1 1 1 i3 (reserved)

index is calculated as: value * 2

Register expression is built as: 

<reg><index>

Example: 

sa68

Specific type of register can be selected with Register Selector RS2

For destination operand op0 specific type of register can be selected with Register Selector Indexable RSI2

Last 4 values are reserved for internal registers i0, i1, i2, i3

Register Index Offset RIO6

5 4 3 2 1 0
rt offset

rt is encoded as Register Selector RS2

offset is calculated as: value * 2

offset is encoded as:

3 2 1 0 offset
0 0 0 0 0
0 0 0 1 2
... ... ... ... ...
1 1 1 0 28
1 1 1 1 30

Register Swizzle RSWZ2

This encoding uses 2 bits to encode the mask.

selector is encoded as:

1 0 meaning
0 0 x
0 1 y
1 0 z
1 1 w

swizzle expression is built as: 

<reg><index>.<swizzle>

Example: 

r22.x

Immediates

Immediate IMM6

Some operands may act as immediate values which are encoded using 6 bits.

Modifier and dest data format

At the moment it is not known which of the data format fields is dest and which is source.

This is the reason why term modifier is mixed with term dest data format.

0x00000000 - 0x08000000

Instructions

mad

Encoding

Lower 4 bytes

7 6 5 4 3 2 1 0
opcode1 data_format predicate
0 0 0 0 0
7 6 5 4 3 2 1 0
swz_alt_op1 alt_opt0 abs_op1 alt_opt2 alt_opt3
x x x
7 6 5 4 3 2 1 0
swz_alt_op3 op3_swz swz_alt_op2 swz_mask
x x x
7 6 5 4 3 2 1 0
swz_en abs_op2 neg_op2 abs_op3 neg_op3 opt1 opt0

Higher 4 bytes

7 6 5 4 3 2 1 0
opt2 opt3 op0
7 6 5 4 3 2 1 0
op0 op2_swz op1_swz op1
7 6 5 4 3 2 1 0
op1 op2
7 6 5 4 3 2 1 0
op2 op3

Notes

x bits do not affect instruction or operands. might affect something else?

swz_mask and swz_en can be combined. what does it give?

what does {} mean ?

Fields (instruction)

data_format:

2 value
0 f32
1 f16

predicate:

1 0 value
0 0
0 1 p0
1 0 !p0
1 1 Pn

Fields (operands)

  • swz_alt_op1 - does not have effect on its own. can be used together with swz_mask to change op1 component to .y . does not have effect with swz_en.

when both swz_mask and swz_en are enabled - changes second component of op1 to .y

  • alt_opt0 - alter opt0. this bit can be combined with opt0 to produce the following modes for op0:
alt_opt0 opt0 value details
1 0 0 sa
1 0 1 {}
1 1 0 index0
1 1 1 index2 mode op0 encodes RIO6. opt0 encodes RSI2
  • abs_op1 - add abs modifier to op1. example: 
    abs(pa38)
  • alt_opt2 - alter opt2. this bit can be combined with opt2 to produce the following modes for op2:
alt_opt2 opt2 value details
1 0 0 index1 mode op2 encodes RIO6. opt2 encodes RSI2
1 0 1 {}
1 1 0 immediate op2 encodes IMM6
1 1 1 index2 mode op2 encodes RIO6. opt2 encodes RSI2
  • alt_opt3 - alter opt3. this bit can be combined with opt3 to produce the following modes for op3:
alt_opt3 opt3 value details
1 0 0 index1 mode op3 encodes RIO6. opt3 encodes RSI2
1 0 1 {}
1 1 0 immediate op3 encodes IMM6
1 1 1 index2 mode op3 encodes RIO6. opt3 encodes RSI2
  • swz_alt_op3 - does not have effect on its own. can be used together with swz_mask to change op3 component to .y . does not have effect with swz_en.

when both swz_mask and swz_en are enabled - changes second component of op3 to .y

  • op3_swz - op3 swizzle Register Swizzle RSWZ2. does not have effect on its own. must be used with swz_en or swz_mask or both.
  • swz_alt_op2 - does not have effect on its own. can be used together with swz_mask to change op2 component to .y . does not have effect with swz_en.
  • swz_mask - changes op0 component to .y . negates each op. enables usage of swizzling mask that is controlled by op1_swz, op2_swz, op3_swz.
  • swz_en - enables usage of swizzling mask that is controlled by op1_swz, op2_swz, op3_swz. swizzle of op0 can not be changed and will allways be .x
  • abs_op2 - add abs modifier to op2. example: 
    abs(pa20)
  • neg_op2 - negate op2. example: 
    -pa86
  • abs_op3 - add abs modifier to op3. example: 
    abs(r20)
  • neg_op3 - negate op3. example: 
    -r86
  • opt1 - when enabled - selects pa register type. when disabled - selects r register type.
  • opt0 - type of operand op0, encoded with Register Selector Indexable RSI2
  • opt2 - type of operand op2, encoded with Register Selector RS2. or Register Selector Indexable RSI2 if specified in alt_opt2.
  • opt3 - type of operand op3, encoded with Register Selector RS2. or Register Selector Indexable RSI2 if specified in alt_opt3.
  • op0 - op0 encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in opt0.

or with Register Index Offset RIO6 using index2 mode if specified in alt_opt0.

or with Register Index Offset RIO6 using index2 mode if specified in alt_opt2. or IMM6 if specified in alt_opt2.

or with Register Index Offset RIO6 using index2 mode if specified in alt_opt3. or IMM6 if specified in alt_opt3.

Swizzles

There are multiple combinations available, controlled by:

  • swizzle fields: op1_swz, op2_swz, op3_swz
  • control bits: swz_en, swz_mask, swz_alt_op1, swz_alt_op2, swz_alt_op3
operand 0 operand 1 operand 2 operand 3
swz_mask swz_en value
0 1 x
swz_mask swz_en swz_alt_op1 op1_swz value
0 1 x 0 0 x
0 1 x 0 1 y
0 1 x 1 0 z
0 1 x 1 1 w
swz_mask swz_en swz_alt_op2 op2_swz value
0 1 x 0 0 x
0 1 x 0 1 y
0 1 x 1 0 z
0 1 x 1 1 w
swz_mask swz_en swz_alt_op3 op3_swz value
0 1 x 0 0 x
0 1 x 0 1 y
0 1 x 1 0 z
0 1 x 1 1 w
operand 0 operand 1 operand 2 operand 3
swz_mask swz_en value
1 0 -y
swz_mask swz_en swz_alt_op1 op1_swz value
1 0 0 0 0 -x
1 0 0 0 1 -y
1 0 0 1 0 -z
1 0 0 1 1 -w
1 0 1 0 0 ?
1 0 1 0 1 ?
1 0 1 1 0 ?
1 0 1 1 1 ?
swz_mask swz_en swz_alt_op2 op2_swz value
1 0 0 0 0 -x
1 0 0 0 1 -y
1 0 0 1 0 -z
1 0 0 1 1 -w
1 0 1 0 0 ?
1 0 1 0 1 ?
1 0 1 1 0 ?
1 0 1 1 1 ?
swz_mask swz_en swz_alt_op3 op3_swz value
1 0 0 0 0 -x
1 0 0 0 1 -y
1 0 0 1 0 -z
1 0 0 1 1 -w
1 0 1 0 0 ?
1 0 1 0 1 ?
1 0 1 1 0 ?
1 0 1 1 1 ?
operand 0 operand 1 operand 2 operand 3
swz_mask swz_en value
1 1 xy
swz_mask swz_en swz_alt_op1 op1_swz value
1 1 0 0 0 xx
1 1 0 0 1 yy
1 1 0 1 0 zz
1 1 0 1 1 ww
swz_mask swz_en swz_alt_op2 op2_swz value
1 1 0 0 0 xx
1 1 0 0 1 yy
1 1 0 1 0 zz
1 1 0 1 1 ww
swz_mask swz_en swz_alt_op3 op3_swz value
1 1 0 0 0 xx
1 1 0 0 1 yy
1 1 0 1 0 zz
1 1 0 1 1 ww

Examples

mad.f32
 
mad.f16

0x08000000 - 0x10000000

Instructions: mul.f32

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
0 0 0 0 1
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 !p0
1 0 1 !p1
1 1 0 !p2
1 1 1 Pn

Examples: 

mul.f32

0x10000000 - 0x18000000

Instructions: mul.f16

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
0 0 0 1 0
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 !p0
1 0 1 !p1
1 1 0 !p2
1 1 1 Pn

Examples: 

mul.f16

0x18000000 - 0x20000000

Instructions: dot.f32, mad.f32

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
0 0 0 1 1
7 6 5 4 3 2 1 0
opcode2
x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

opcode2:

5 value
0 dot.f32
1 mad.f32

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 !p0
1 0 1 !p1
1 1 0 !p2
1 1 1 Pn

Examples: 

dot.f32

mad.f32

0x20000000 - 0x28000000

Instructions: dot, mov, rsq, rcp, exp, log

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
0 0 1 0 0 x
7 6 5 4 3 2 1 0
op_sel data_format
x x x x x x
7 6 5 4 3 2 1 0
opcode2
x 1 x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Notes:

Having bit 3 in byte 2 set to 0 produces invalid instruction

Fields:

data_format:

5 value
0 f32
1 f16

predicate:

1 0 value
0 0
0 1 p0
1 0 !p0
1 1 Pn

opcode2 (depends on op_sel):

op_sel 6 5 4 value
0 0 0 0 invalid
0 0 0 1 invalid
0 0 1 0 dot
0 0 1 1 invalid
0 1 0 0 invalid
0 1 0 1 mov
0 1 1 0 rsq
0 1 1 1 rcp
op_sel 6 5 4 value
1 0 0 0 invalid
1 0 0 1 invalid
1 0 1 0 invalid
1 0 1 1 invalid
1 1 0 0 exp
1 1 0 1 log
1 1 1 0 invalid
1 1 1 1 invalid

Examples: 

dot.f32
mov.f32
rsq.f32
rcp.f32
exp.f32
log.f32

dot.f16
mov.f16
rsq.f16
rcp.f16
exp.f16
log.f16

0x28000000 - 0x30000000

Instructions: dot, mov, rsq, rcp

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
0 0 1 0 1 x
7 6 5 4 3 2 1 0
data_format
x x x x x x x
7 6 5 4 3 2 1 0
opcode2
x 1 x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Notes:

Having bit 3 in byte 2 set to 0 produces invalid instruction

Fields:

data_format:

5 value
0 f32
1 f16

predicate:

1 0 value
0 0
0 1 p0
1 0 !p0
1 1 Pn

opcode2:

6 5 4 value
0 0 0 invalid
0 0 1 invalid
0 1 0 dot
0 1 1 invalid
1 0 0 invalid
1 0 1 mov
1 1 0 rsq
1 1 1 rcp

Examples: 

dot.f32
mov.f32
rsq.f32
rcp.f32

dot.f16
mov.f16
rsq.f16
rcp.f16

0x30000000 - 0x38000000

Instructions: rcp, rsq, log, exp

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
0 0 1 1 0
7 6 5 4 3 2 1 0
data_format
x x x x x x
7 6 5 4 3 2 1 0
opcode2 modifier
x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Notes:

modifier should be omitted if data_format matches modifier.

Fields:

opcode2:

2 1 value
0 0 rcp
0 1 rsq
1 0 log
1 1 exp

data_format:

6 5 value
0 0 f32
0 1 f16
1 0 fx10
1 1 invalid

modifier:

0 value
0 f32
1 fx10

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 p3
1 0 1 !p0
1 1 0 !p1
1 1 1 Pn

Examples: 

rcp.f32
rsq.f32
log.f32
exp.f32

rcp.f32.fx10
rsq.f32.fx10
log.f32.fx10
exp.f32.fx10

rcp.f16.f32
rsq.f16.f32
log.f16.f32
exp.f16.f32

rcp.f16.fx10
rsq.f16.fx10
log.f16.fx10
exp.f16.fx10

rcp.fx10.f32
rsq.fx10.f32
log.fx10.f32
exp.fx10.f32

rcp.fx10
rsq.fx10
log.fx10
exp.fx10

0x38000000 - 0x40000000

Instructions: mov, cmov, cmov8

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
0 0 1 1 1
7 6 5 4 3 2 1 0
cond
x x x x x x x
7 6 5 4 3 2 1 0
opcode2 data_format
x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Notes:

cond is only applicable to cmov and cmov8 since this is conditional move.

Fields:

opcode2:

7 6 value
0 0 mov
0 1 cmov
1 0 cmov8
1 1 invalid

cond:

6 value
0 eqzero
1 ltzero

data_format:

2 1 0 value
0 0 0 i8
0 0 1 i16
0 1 0 i32
0 1 1 fx10
1 0 0 f16
1 0 1 f32
1 1 0 invalid
1 1 1 invalid

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 p3
1 0 1 !p0
1 1 0 !p1
1 1 1 Pn

Examples: 

mov.i8
mov.i16
mov.i32
mov.fx10
mov.f16
mov.f32

cmov.eqzero.i8
cmov.eqzero.i16
cmov.eqzero.i32
cmov.eqzero.fx10
cmov.eqzero.f16
cmov.eqzero.f32

cmov8.eqzero.i8
cmov8.eqzero.i16
cmov8.eqzero.i32
cmov8.eqzero.fx10
cmov8.eqzero.f16
cmov8.eqzero.f32

cmov.ltzero.i8
cmov.ltzero.i16
cmov.ltzero.i32
cmov.ltzero.fx10
cmov.ltzero.f16
cmov.ltzero.f32

cmov8.ltzero.i8
cmov8.ltzero.i16
cmov8.ltzero.i32
cmov8.ltzero.fx10
cmov8.ltzero.f16
cmov8.ltzero.f32

0x40000000 - 0x48000000

Instructions: pack, (mov)

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
0 1 0 0 0
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
modifier data_format
x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Notes:

when modifier matches data_format it shall be omitted since it has no effect in terms of packing.

furthermore instruction mnemonic shall be replaced to mov

Fields:

data_format:

0 value
0 u8
1 s16

modifier:

3 2 1 value
0 0 0 u8
0 0 1 s8
0 1 0 o8
0 1 1 u16
1 0 0 s16
1 0 1 f16
1 1 0 f32
1 1 1 invalid

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 p3
1 0 1 !p0
1 1 0 !p1
1 1 1 Pn

Examples: 

mov.u8
pack.s16.u8
pack.u8.s8
pack.s16.s8
pack.u8.o8
pack.s16.o8
pack.u8.u16
pack.s16.u16
pack.u8.s16
mov.s16
pack.u8.f16
pack.s16.f16
pack.u8.f32
pack.s16.f32

0x48000000 - 0x50000000

Instructions: this group only contains illegal instructions

Encoding:

7 6 5 4 3 2 1 0
opcode1
0 1 0 0 1 x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

0x50000000 - 0x58000000

Instructions: and.u32

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
0 1 0 1 0
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 p3
1 0 1 !p0
1 1 0 !p1
1 1 1 Pn

Examples: 

and.u32

0x58000000 - 0x60000000

Instructions: xor.u32

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
0 1 0 1 1
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 p3
1 0 1 !p0
1 1 0 !p1
1 1 1 Pn

Examples: 

xor.u32

0x60000000 - 0x68000000

Instructions: shl.u32

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
0 1 1 0 0
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 p3
1 0 1 !p0
1 1 0 !p1
1 1 1 Pn

Examples: 

shl.u32

0x68000000 - 0x70000000

Instructions: shr.u32

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
0 1 1 0 1 x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 p3
1 0 1 !p0
1 1 0 !p1
1 1 1 Pn

Examples: 

shr.u32

0x70000000 - 0x78000000

Instructions: rlp.u32

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
0 1 1 1 0 x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 p3
1 0 1 !p0
1 1 0 !p1
1 1 1 Pn

Examples: 

rlp.u32

0x78000000 - 0x80000000

Instructions: this group only contains illegal instructions

Encoding:

7 6 5 4 3 2 1 0
opcode1
0 1 1 1 1 x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

0x80000000 - 0x88000000

Instructions: add.fx8

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
1 0 0 0 0 x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

predicate:

2 1 value
0 0
0 1 p0
1 0 p1
1 1 !p0

Examples: 

add.fx8

0x88000000 - 0x90000000

Instructions: add.fx8, sub.fx8

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
1 0 0 0 1 x
7 6 5 4 3 2 1 0
opcode2
x x x x x x
7 6 5 4 3 2 1 0
x x x x 0 0 x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Notes:

Having bits 2, 3 in byte 2 set to 1 produces invalid instruction

Fields:

opcode2:

5 4 value
0 0 add.fx8
0 1 sub.fx8
1 0 invalid
1 1 invalid

predicate:

2 1 value
0 0
0 1 p0
1 0 p1
1 1 !p0

Examples: 

add.fx8

sub.fx8

0x90000000 - 0x98000000

Instructions: add.fx8, sub.fx8, min.fx8, max.fx8

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
1 0 0 1 0 x
7 6 5 4 3 2 1 0
opcode2
x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x 0
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Notes:

Having bit 0 in byte 2 set to 1 produces invalid instruction

Fields:

opcode2:

5 4 value
0 0 add.fx8
0 1 sub.fx8
1 0 min.fx8
1 1 max.fx8

predicate:

2 1 value
0 0
0 1 p0
1 0 p1
1 1 !p0

Examples: 

add.fx8

sub.fx8

min.fx8

max.fx8

0x98000000 - 0xA0000000

Instructions: mad.u8

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
1 0 0 1 1 x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
modifier
x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

modifier:

3 value
0
1 sat

predicate:

2 1 value
0 0
0 1 p0
1 0 p1
1 1 !p0

Examples: 

mad.u8
mad.sat.u8

0xA0000000 - 0xA8000000

Instructions: mad

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
1 0 1 0 0 x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
data_format modifier
x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

data_format:

3 value
0 u16
1 i16

modifier:

2 value
0
1 sat

predicate:

2 1 value
0 0
0 1 p0
1 0 p1
1 1 !p0

Examples: 

mad.u16
mad.u16.sat
mad.i16
mad.i16.sat

0xA8000000 - 0xB0000000

Instructions: mad

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
1 0 1 0 1 x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
data_format modifier
x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

data_format:

3 value
0 u32
1 i32

modifier:

2 value
0
1 sat

predicate:

2 1 value
0 0
0 1 p0
1 0 p1
1 1 !p0

Examples: 

mad.u32
mad.u32.sat
mad.i32
mad.i32.sat

0xB0000000 - 0xB8000000

Instructions: this group only contains illegal instructions

Encoding:

7 6 5 4 3 2 1 0
opcode1
1 0 1 1 0 x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

0xB8000000 - 0xC0000000

Instructions: this group only contains illegal instructions

Encoding:

7 6 5 4 3 2 1 0
opcode1
1 0 1 1 1 x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

0xC0000000 - 0xC8000000

Instructions: this group only contains illegal instructions

Encoding:

7 6 5 4 3 2 1 0
opcode1
1 1 0 0 0 x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

0xC8000000 - 0xD0000000

Instructions: mad.u8

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
1 1 0 0 1 x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
modifier
x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

modifier:

3 value
0
1 sat

predicate:

2 1 value
0 0
0 1 p0
1 0 p1
1 1 !p0

Examples: 

mad.u8
mad.sat.u8

0xD0000000 - 0xD8000000

Instructions: mad

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
1 1 0 1 0
7 6 5 4 3 2 1 0
modifier
x x 0 x x x x
7 6 5 4 3 2 1 0
data_format
x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Notes:

Having bit 5 in byte 1 set to 1 produces invalid instruction

Fields:

modifier:

4 value
0 s0
1 s1

data_format:

1 value
0 u32
1 i32

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 p3
1 0 1 !p0
1 1 0 !p1
1 1 1 Pn

Examples: 

mad.u32.s0
mad.i32.s0

mad.u32.s1
mad.i32.s1

0xD8000000 - 0xE0000000

Instructions: this group only contains illegal instructions

Encoding:

7 6 5 4 3 2 1 0
opcode1
1 1 0 1 1 x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
x x x x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

0xE0000000 - 0xE8000000

Instructions: tex

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
1 1 1 0 0 0 0 0
7 6 5 4 3 2 1 0
modifier
x x x x x x x
7 6 5 4 3 2 1 0
data_format dim func
x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

dim:

3 2 value
0 0 1D
0 1 2D
1 0 Cube
1 1 invalid

func:

1 0 value
0 0
0 1 Bias
1 0 Replace
1 1 Grad

modifier:

3 value
0
1 minp

data_format:

7 6 value
0 0
0 1 invalid
1 0 f16
1 1 f32

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 p3
1 0 1 !p0
1 1 0 !p1
1 1 1 Pn

Examples: 

tex1D
tex1D.f16
tex1D.f32
tex1D.minp
tex1D.minp.f16
tex1D.minp.f32

tex1DBias
tex1DBias.f16
tex1DBias.f32
tex1DBias.minp
tex1DBias.minp.f16
tex1DBias.minp.f32

tex1DReplace
tex1DReplace.f16
tex1DReplace.f32
tex1DReplace.minp
tex1DReplace.minp.f16
tex1DReplace.minp.f32

tex1DGrad
tex1DGrad.f16
tex1DGrad.f32
tex1DGrad.minp
tex1DGrad.minp.f16
tex1DGrad.minp.f32

tex2D
tex2D.f16
tex2D.f32
tex2D.minp
tex2D.minp.f16
tex2D.minp.f32

tex2DBias
tex2DBias.f16
tex2DBias.f32
tex2DBias.minp
tex2DBias.minp.f16
tex2DBias.minp.f32

tex2DReplace
tex2DReplace.f16
tex2DReplace.f32
tex2DReplace.minp
tex2DReplace.minp.f16
tex2DReplace.minp.f32

tex2DGrad
tex2DGrad.f16
tex2DGrad.f32
tex2DGrad.minp
tex2DGrad.minp.f16
tex2DGrad.minp.f32

texCube
texCube.f16
texCube.f32
texCube.minp
texCube.minp.f16
texCube.minp.f32

texCubeBias
texCubeBias.f16
texCubeBias.f32
texCubeBias.minp
texCubeBias.minp.f16
texCubeBias.minp.f32

texCubeReplace
texCubeReplace.f16
texCubeReplace.f32
texCubeReplace.minp
texCubeReplace.minp.f16
texCubeReplace.minp.f32

texCubeGrad
texCubeGrad.f16
texCubeGrad.f32
texCubeGrad.minp
texCubeGrad.minp.f16
texCubeGrad.minp.f32

0xE8000000 - 0xF0000000

Instructions: lda32, ldl32, ldt32

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
1 1 1 0 1
7 6 5 4 3 2 1 0
modifier
x x x x x x x
7 6 5 4 3 2 1 0
index opcode2
x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Notes:

index is only applicable when fetch modifier is specified

Fields:

modifier:

5 value
0 fetch
1

index:

7 6 5 4 value
0 0 0 0 1
0 0 0 1 2
0 0 1 0 3
0 0 1 1 4
0 1 0 0 5
0 1 0 1 6
0 1 1 0 7
0 1 1 1 8
1 0 0 0 9
1 0 0 1 10
1 0 1 0 11
1 0 1 1 12
1 1 0 0 13
1 1 0 1 14
1 1 1 0 15
1 1 1 1 16

opcode2:

3 2 value
0 0 lda32
0 1 ldl32
1 0 ldt32
1 1 invalid

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 p3
1 0 1 !p0
1 1 0 !p1
1 1 1 Pn

Examples: 

lda32
ldl32
ldt32

lda32.fetch1
lda32.fetch2
lda32.fetch3
lda32.fetch4
lda32.fetch5
lda32.fetch6
lda32.fetch7
lda32.fetch8
lda32.fetch9
lda32.fetch10
lda32.fetch11
lda32.fetch12
lda32.fetch13
lda32.fetch14
lda32.fetch15
lda32.fetch16

ldl32.fetch1
ldl32.fetch2
ldl32.fetch3
ldl32.fetch4
ldl32.fetch5
ldl32.fetch6
ldl32.fetch7
ldl32.fetch8
ldl32.fetch9
ldl32.fetch10
ldl32.fetch11
ldl32.fetch12
ldl32.fetch13
ldl32.fetch14
ldl32.fetch15
ldl32.fetch16

ldt32.fetch1
ldt32.fetch2
ldt32.fetch3
ldt32.fetch4
ldt32.fetch5
ldt32.fetch6
ldt32.fetch7
ldt32.fetch8
ldt32.fetch9
ldt32.fetch10
ldt32.fetch11
ldt32.fetch12
ldt32.fetch13
ldt32.fetch14
ldt32.fetch15
ldt32.fetch16

0xF0000000 - 0xF8000000

Instructions: sta32, stl32, stt32

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
1 1 1 1 0
7 6 5 4 3 2 1 0
modifier
x x x x x x x
7 6 5 4 3 2 1 0
index opcode2
x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Notes:

index is only applicable when fetch modifier is specified

Fields:

modifier:

5 value
0 fetch
1

index:

7 6 5 4 value
0 0 0 0 1
0 0 0 1 2
0 0 1 0 3
0 0 1 1 4
0 1 0 0 5
0 1 0 1 6
0 1 1 0 7
0 1 1 1 8
1 0 0 0 9
1 0 0 1 10
1 0 1 0 11
1 0 1 1 12
1 1 0 0 13
1 1 0 1 14
1 1 1 0 15
1 1 1 1 16

opcode2:

3 2 value
0 0 sta32
0 1 stl32
1 0 stt32
1 1 invalid

predicate:

2 1 0 value
0 0 0
0 0 1 p0
0 1 0 p1
0 1 1 p2
1 0 0 p3
1 0 1 !p0
1 1 0 !p1
1 1 1 Pn

Examples: 

sta32
stl32
stt32

sta32.fetch1
sta32.fetch2
sta32.fetch3
sta32.fetch4
sta32.fetch5
sta32.fetch6
sta32.fetch7
sta32.fetch8
sta32.fetch9
sta32.fetch10
sta32.fetch11
sta32.fetch12
sta32.fetch13
sta32.fetch14
sta32.fetch15
sta32.fetch16

stl32.fetch1
stl32.fetch2
stl32.fetch3
stl32.fetch4
stl32.fetch5
stl32.fetch6
stl32.fetch7
stl32.fetch8
stl32.fetch9
stl32.fetch10
stl32.fetch11
stl32.fetch12
stl32.fetch13
stl32.fetch14
stl32.fetch15
stl32.fetch16

stt32.fetch1
stt32.fetch2
stt32.fetch3
stt32.fetch4
stt32.fetch5
stt32.fetch6
stt32.fetch7
stt32.fetch8
stt32.fetch9
stt32.fetch10
stt32.fetch11
stt32.fetch12
stt32.fetch13
stt32.fetch14
stt32.fetch15
stt32.fetch16

0xF8000000 - 0xFF000000

Notes:

this instruction group is much more complex than others so description is given in form of "glued" truth tables instead of independent truth tables.

predicate 000

Instructions:

Encoding:

7 6 5 4 3 2 1 0
opcode1 predicate
1 1 1 1 1 0 0 0
7 6 5 4 3 2 1 0
modifier1 opcode2
x x x x
7 6 5 4 3 2 1 0
opcode4 modifier2 opcode3
x x x x x
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

Fields:

opcode2:

predicate modifier1 opcode3 opcode4 modifier2 5 4 3 value
0 0 0 0 0 x 0 0 0 0 ba
0 0 0 0 1 x 0 0 0 0 mov
0 0 0 0 0 x 1 0 0 0 ba.savelink
0 0 0 0 1 x 1 0 0 0 mov
0 0 0 0 0 x x 0 0 1 mov.f32
0 0 0 0 1 x x 0 0 1 mov
0 0 0 0 x x x 0 1 x mov.f32
0 0 0 0 x x x 1 0 x mov.f32
0 0 0 0 x 0 x 1 1 x pcoeff
0 0 0 0 x 1 x 1 1 x ptoff
predicate modifier1 opcode4 5 4 3 value
0 0 0 1 x 0 0 x invalid
0 0 0 1 x 0 1 x invalid
0 0 0 1 x 1 0 x mov.f32
0 0 0 1 0 1 1 x pcoeff
0 0 0 1 1 1 1 x ptoff

Examples: 



predicate 001


Instructions: 

Encoding













7
6
5
4
3
2
1
0




opcode1
predicate




1
1
1
1
1
0
0
1









7
6
5
4
3
2
1
0





modifier1
opcode2





x




x
x
x









7
6
5
4
3
2
1
0





sub_pred





x
x
x
x
x


x





modifier2
opcode3




x
x
x
x
x
x











7
6
5
4
3
2
1
0
















?
?
?
?
?
?
?
?





Notes:

predicate does not apply to all instructions

Fields

opcode2:













predicate
modifier1
opcode3
modifier2
sub_pred
5
4
3
value




0
0
1
0
0
0
x
x
0
0
0
p0 ba




0
0
1
0
1
0
x
x
0
0
0
p0 mov




0
0
1
0
0
1
x
x
0
0
0
p0 ba.savelink




0
0
1
0
1
1
x
x
0
0
0
p0 mov




0
0
1
0
0
x
x
x
0
0
1
mov.f32




0
0
1
0
1
x
x
x
0
0
1
p0 mov




0
0
1
0
x
x
x
x
0
1
x
mov.f32




0
0
1
0
x
x
x
x
1
0
x
mov.f32




0
0
1
0
x
x
0
0
1
1
x
kill




0
0
1
0
x
x
0
1
1
1
x
!p0 kill




0
0
1
0
x
x
1
0
1
1
x
!p1 kill




0
0
1
0
x
x
1
1
1
1
x
p0 kill









predicate
modifier1
sub_pred
5
4
3
value




0
0
1
1
x
x
0
0
x
invalid




0
0
1
1
x
x
0
1
x
invalid




0
0
1
1
x
x
1
0
x
mov.f32




0
0
1
1
0
0
1
1
x
kill




0
0
1
1
0
1
1
1
x
!p0 kill




0
0
1
1
1
0
1
1
x
!p1 kill




0
0
1
1
1
1
1
1
x
p0 kill





Examples:





predicate 010


Instructions: 

Encoding:













7
6
5
4
3
2
1
0




opcode1
predicate




1
1
1
1
1
0
1
0









7
6
5
4
3
2
1
0




modifier1
opcode2
opcode4











x
x




modifier1
opcode2










x
x
x









7
6
5
4
3
2
1
0





opcode5
opcode6




x
x
x










modifier2
opcode3




x
x
x
x
x
x











7
6
5
4
3
2
1
0
















?
?
?
?
?
?
?
?





Notes:

predicate does not apply to all instructions

Fields

opcode2













predicate
modifier1
opcode3
modifier2
5
4
3
value




0
1
0
0
0
0
0
0
0
0
p1 ba




0
1
0
0
0
1
0
0
0
0
p1 mov




0
1
0
0
0
0
1
0
0
0
p1 ba.savelink




0
1
0
0
0
1
1
0
0
0
p1 mov




0
1
0
0
0
0
x
0
0
1
mov.f32




0
1
0
0
0
1
x
0
0
1
p1	mov




0
1
0
0
0
x
x
0
1
x
mov.f32




0
1
0
0
0
x
x
1
0
x
mov.f32




0
1
0
0
0
x
x
1
1
x
invalid











predicate
modifier1
opcode4
opcode5
opcode6
5
4
3
value




0
1
0
0
1
0
x
x
x
x
x
0
0
x
mov.f32




0
1
0
0
1
1
0
x
0
0
x
0
0
x
mov.f32




0
1
0
0
1
1
0
x
0
1
0
0
0
x
mov.f32




0
1
0
0
1
1
0
x
0
1
1
0
0
x
invalid




0
1
0
0
1
1
0
x
1
0
x
0
0
x
invalid




0
1
0
0
1
1
0
x
1
1
0
0
0
x
invalid




0
1
0
0
1
1
0
x
1
1
1
0
0
x
mov.f32




0
1
0
0
1
1
1
0
0
0
x
0
0
x
mov.f32




0
1
0
0
1
1
1
0
0
1
0
0
0
x
mov.f32




0
1
0
0
1
1
1
0
0
1
1
0
0
x
invalid




0
1
0
0
1
1
1
0
1
0
x
0
0
x
invalid




0
1
0
0
1
1
1
0
1
1
0
0
0
x
invalid




0
1
0
0
1
1
1
0
1
1
1
0
0
x
mov.f32




0
1
0
0
1
1
1
1
x
x
x
0
0
x
invalid




0
1
0
0
1
x
x
x
x
x
x
0
1
x
invalid




0
1
0
0
1
x
x
x
x
x
x
1
0
x
mov.f32




0
1
0
0
1
x
x
x
x
x
x
1
1
x
invalid

















predicate
modifier1
opcode3
modifier2
5
4
3
value




0
1
0
1
0
0
0
0
0
0
p1 ba




0
1
0
1
0
1
0
0
0
0
p1 mov




0
1
0
1
0
0
1
0
0
0
p1 ba.savelink




0
1
0
1
0
1
1
0
0
0
p1 mov




0
1
0
1
0
0
x
0
0
1
mov.f32




0
1
0
1
0
1
x
0
0
1
p1	mov




0
1
0
1
0
x
x
0
1
x
mov.f32




0
1
0
1
0
x
x
1
0
x
mov.f32




0
1
0
1
0
x
x
1
1
x
invalid











predicate
modifier1
5
4
3
value




0
1
0
1
1
0
0
x
mov.f32




0
1
0
1
1
0
1
x
invalid




0
1
0
1
1
1
0
x
mov.f32




0
1
0
1
1
1
1
x
invalid







Examples:





predicate 011


Instructions: 

Encoding













7
6
5
4
3
2
1
0




opcode1
predicate




1
1
1
1
1
0
1
1









7
6
5
4
3
2
1
0





modifier1
opcode2





x




x
x
x









7
6
5
4
3
2
1
0





sub_pred





x
x
x
x
x


x




opcode4
opcode5

modifier2
opcode3








x
x











7
6
5
4
3
2
1
0
















?
?
?
?
?
?
?
?





Notes:

predicate does not apply to all instructions

Fields

opcode2













predicate
modifier1
opcode3
modifier2
opcode4
opcode5
sub_pred
5
4
3
value




0
1
1
0
0
0
x
x
x
x
x
x
0
0
0
p2 ba




0
1
1
0
1
0
x
x
x
x
x
x
0
0
0
p2 mov




0
1
1
0
0
1
x
x
x
x
x
x
0
0
0
p2 ba.savelink




0
1
1
0
1
1
x
x
x
x
x
x
0
0
0
p2 mov




0
1
1
0
0
x
x
x
x
x
x
x
0
0
1
mov.f32




0
1
1
0
1
x
x
x
x
x
x
x
0
0
1
p2 mov




0
1
1
0
x
x
x
x
x
x
x
x
0
1
x
mov.f32




0
1
1
0
x
x
0
0
0
x
x
x
1
0
x
mov.f32




0
1
1
0
x
x
0
0
1
x
x
x
1
0
x
mov.f32




0
1
1
0
x
x
0
1
0
x
x
x
1
0
x
mov.f32




0
1
1
0
x
x
0
1
1
0
x
x
1
0
x
mov.f32




0
1
1
0
x
x
0
1
1
1
x
x
1
0
x
invalid




0
1
1
0
x
x
1
0
0
x
x
x
1
0
x
mov.f32




0
1
1
0
x
x
1
0
1
x
x
x
1
0
x
mov.f32




0
1
1
0
x
x
1
1
0
x
x
x
1
0
x
invalid




0
1
1
0
x
x
1
1
1
x
x
x
1
0
x
invalid




0
1
1
0
x
x
x
x
x
x
0
0
1
1
x
depthf




0
1
1
0
x
x
x
x
x
x
0
1
1
1
x
p0 depthf




0
1
1
0
x
x
x
x
x
x
1
0
1
1
x
p1 depthf




0
1
1
0
x
x
x
x
x
x
1
1
1
1
x
!p0 depthf











predicate
modifier1
opcode4
opcode5
sub_pred
5
4
3
value




0
1
1
1
x
x
x
x
x
x
0
0
x
invalid




0
1
1
1
x
x
x
x
x
x
0
1
x
invalid




0
1
1
1
0
0
0
x
x
x
1
0
x
mov.f32




0
1
1
1
0
0
1
x
x
x
1
0
x
mov.f32




0
1
1
1
0
1
0
x
x
x
1
0
x
mov.f32




0
1
1
1
0
1
1
0
x
x
1
0
x
mov.f32




0
1
1
1
0
1
1
1
x
x
1
0
x
invalid




0
1
1
1
1
0
0
x
x
x
1
0
x
mov.f32




0
1
1
1
1
0
1
x
x
x
1
0
x
mov.f32




0
1
1
1
1
1
0
x
x
x
1
0
x
invalid




0
1
1
1
1
1
1
x
x
x
1
0
x
invalid




0
1
1
1
x
x
x
x
0
0
1
1
x
depthf




0
1
1
1
x
x
x
x
0
1
1
1
x
p0 depthf




0
1
1
1
x
x
x
x
1
0
1
1
x
p1 depthf




0
1
1
1
x
x
x
x
1
1
1
1
x
!p0 depthf







Examples:





predicate 100


Instructions: 

Encoding













7
6
5
4
3
2
1
0




opcode1
predicate




1
1
1
1
1
1
0
0









7
6
5
4
3
2
1
0





modifier1
opcode2





x




x
x
x









7
6
5
4
3
2
1
0





sub_pred





x
x
x
x



x





modifier2
opcode3




x
x
x
x
x
x











7
6
5
4
3
2
1
0
















?
?
?
?
?
?
?
?





Notes:

predicate does not apply to all instructions

Fields

opcode2:













predicate
modifier1
opcode3
modifier2
sub_pred
5
4
3
value




1
0
0
0
0
0
x
x
x
0
0
0
p3 ba




1
0
0
0
1
0
x
x
x
0
0
0
p3 mov




1
0
0
0
0
1
x
x
x
0
0
0
p3 ba.savelink




1
0
0
0
1
1
x
x
x
0
0
0
p3 mov




1
0
0
0
0
x
x
x
x
0
0
1
mov.f32




1
0
0
0
1
x
x
x
x
0
0
1
p3 mov




1
0
0
0
x
x
x
x
x
0
1
x
mov.f32




1
0
0
0
x
x
0
0
0
1
0
x
mov.u32




1
0
0
0
x
x
0
0
1
1
0
x
p0 mov.u32




1
0
0
0
x
x
0
1
0
1
0
x
p1 mov.u32




1
0
0
0
x
x
0
1
1
1
0
x
p2 mov.u32




1
0
0
0
x
x
1
0
0
1
0
x
p3 mov.u32




1
0
0
0
x
x
1
0
1
1
0
x
!p0 mov.u32




1
0
0
0
x
x
1
1
0
1
0
x
!p1 mov.u32




1
0
0
0
x
x
1
1
1
1
0
x
Pn mov.u32




1
0
0
0
x
x
x
x
x
1
1
x
invalid











predicate
modifier1
sub_pred
5
4
3
value




1
0
0
1
x
x
x
0
0
x
invalid




1
0
0
1
x
x
x
0
1
x
invalid




1
0
0
1
0
0
0
1
0
x
mov.u32




1
0
0
1
0
0
1
1
0
x
p0 mov.u32




1
0
0
1
0
1
0
1
0
x
p1 mov.u32




1
0
0
1
0
1
1
1
0
x
p2 mov.u32




1
0
0
1
1
0
0
1
0
x
p3 mov.u32




1
0
0
1
1
0
1
1
0
x
!p0 mov.u32




1
0
0
1
1
1
0
1
0
x
!p1 mov.u32




1
0
0
1
1
1
1
1
0
x
Pn mov.u32




1
0
0
1
x
x
x
1
1
x
invalid







Examples:





predicate 101


Instructions: 

Encoding













7
6
5
4
3
2
1
0




opcode1
predicate




1
1
1
1
1
1
0
1









7
6
5
4
3
2
1
0





modifier1
opcode2





x




x
x
x









7
6
5
4
3
2
1
0





modifier2
opcode3




x
x
x
x
x
x











7
6
5
4
3
2
1
0
















?
?
?
?
?
?
?
?





Notes:

predicate does not apply to all instructions

Fields

opcode2:













predicate
modifier1
opcode3
modifier2
5
4
3
value




1
0
1
0
0
0
0
0
0
!p0 ba




1
0
1
0
1
0
0
0
0
!p0 mov




1
0
1
0
0
1
0
0
0
!p0 ba.savelink




1
0
1
0
1
1
0
0
0
!p0 mov




1
0
1
0
0
x
0
0
1
mov.f32




1
0
1
0
1
x
0
0
1
!p0 mov




1
0
1
0
x
x
0
1
x
mov.f32




1
0
1
0
x
x
1
0
x
mov.f32




1
0
1
0
x
x
1
1
x
invalid











predicate
modifier1
5
4
3
value




1
0
1
1
0
0
x
invalid




1
0
1
1
0
1
x
invalid




1
0
1
1
1
0
x
mov.f32




1
0
1
1
1
1
x
invalid







Examples:





predicate 110


Instructions: 

Encoding













7
6
5
4
3
2
1
0




opcode1
predicate




1
1
1
1
1
1
1
0









7
6
5
4
3
2
1
0





modifier1
opcode2





x




x
x
x









7
6
5
4
3
2
1
0





modifier2
opcode3




x
x
x
x
x
x











7
6
5
4
3
2
1
0
















?
?
?
?
?
?
?
?





Notes:

predicate does not apply to all instructions

Fields

opcode2:













predicate
modifier1
opcode3
modifier2
5
4
3
value




1
1
0
0
0
0
0
0
0
!p1 ba




1
1
0
0
1
0
0
0
0
!p1 mov




1
1
0
0
0
1
0
0
0
!p1 ba.savelink




1
1
0
0
1
1
0
0
0
!p1 mov




1
1
0
0
0
x
0
0
1
mov.f32




1
1
0
0
1
x
0
0
1
!p1 mov




1
1
0
0
x
x
0
1
x
invalid




1
1
0
0
x
x
1
0
x
mov.f32




1
1
0
0
x
x
1
1
x
invalid











predicate
modifier1
5
4
3
value




1
1
0
1
0
0
x
invalid




1
1
0
1
0
1
x
invalid




1
1
0
1
1
0
x
mov.f32




1
1
0
1
1
1
x
invalid







Examples:





predicate 111


Instructions: 

Encoding













7
6
5
4
3
2
1
0




opcode1
predicate




1
1
1
1
1
1
1
1









7
6
5
4
3
2
1
0





modifier1
opcode2





x




x
x
x









7
6
5
4
3
2
1
0





modifier2
opcode3




x
x
x
x
x
x











7
6
5
4
3
2
1
0
















?
?
?
?
?
?
?
?





Notes:

predicate does not apply to all instructions

Fields

opcode2:













predicate
modifier1
opcode3
modifier2
5
4
3
value




1
1
1
0
0
0
0
0
0
Pn ba




1
1
1
0
1
0
0
0
0
Pn mov




1
1
1
0
0
1
0
0
0
Pn ba.savelink




1
1
1
0
1
1
0
0
0
Pn mov




1
1
1
0
0
x
0
0
1
mov.f32




1
1
1
0
1
x
0
0
1
Pn mov




1
1
1
0
x
x
0
1
x
invalid




1
1
1
0
x
x
1
0
x
mov.f32




1
1
1
0
x
x
1
1
x
invalid











predicate
modifier1
5
4
3
value




1
1
1
1
0
0
x
invalid




1
1
1
1
0
1
x
invalid




1
1
1
1
1
0
x
mov.f32




1
1
1
1
1
1
x
invalid







Examples:





Retrieved from "http://wiki.henkaku.xyz/index.php?title=SGX543&oldid=5983"