SPI Registers: Difference between revisions
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| Line 29: | Line 29: | ||
| 4 | | 4 | ||
| Write FIFO | | Write FIFO | ||
|- | |||
| 0x08 | |||
| 4 | |||
| Configuration | |||
|- | |- | ||
| 0x10 | | 0x10 | ||
Revision as of 13:32, 28 July 2018
MMIO Interfaces
| Name | Physical address |
|---|---|
| SceSpi0Reg (SceSyscon) | 0xE0A00000 |
| SceSpi1Reg (SceMotionDev) | 0xE0A10000 |
| SceSpi2Reg (SceOled) | 0xE0A20000 |
Registers
| Offset | Size | Description |
|---|---|---|
| 0x00 | 4 | Read FIFO |
| 0x04 | 4 | Write FIFO |
| 0x08 | 4 | Configuration |
| 0x10 | 4 | Start transfer (write 0b1), cancel transfer(write 0b0), transfer busy (reads bit0 = 0)? |
| 0x18 | 4 | Start transfer (bit 0 or 1), transfer direction (bit 0 or 1)? |
| 0x24 | 4 | Flags? |
| 0x28 | 4 | Number of available bytes to read from the FIFO |
| 0x2C | 4 | Number of pending bytes in the write the FIFO (maximum = 0x7F) |