Main Processor

Main SoC

See Kermit.

Cortex A9 MPcore

The custom SoC includes the ARM Cortex-A9 MPCore as its CPU, mounting four little-endian ARM Cortex-A9 processor cores, which is common in modern high performance embedded devices like cell phones and tablets. The PSVita cores have a MIDR value of 0x412FC09A, meaning it is Cortex-A9 r2p10. Indeed there are usage of undocumented CP15 registers.

Register	Name	Description
p15, #0, r0, c0, c0, #0	MIDR	Main ID Register
p15, #0, r0, c0, c0, #1	CTR	Cache Type Register
p15, #0, r0, c0, c0, #2	TCMTR	TCM Type Register
p15, #0, r0, c0, c0, #3	TLBTR	TLB Type Register
p15, #0, r0, c0, c0, #5	MPIDR	Multiprocessor Affinity Register
p15, #0, r0, c0, c0, #6	REVIDR	Revision ID Register
p15, #0, r0, c0, c1, #0	ID_PFR0	Processor Feature Register 0
p15, #0, r0, c0, c1, #1	ID_PFR1	Processor Feature Register 1
p15, #0, r0, c0, c1, #2	ID_DFR0	Debug Feature Register 0
p15, #0, r0, c0, c1, #3	ID_AFR0	Auxiliary Feature Register 0
p15, #0, r0, c0, c1, #4	ID_MMFR0	Memory Model Feature Register 0
p15, #0, r0, c0, c1, #5	ID_MMFR1	Memory Model Feature Register 1
p15, #0, r0, c0, c1, #6	ID_MMFR2	Memory Model Feature Register 2
p15, #0, r0, c0, c1, #7	ID_MMFR3	Memory Model Feature Register 3
p15, #0, r0, c0, c2, #0	ID_ISAR0	Instruction Set Attribute Register 0
p15, #0, r0, c0, c2, #1	ID_ISAR1	Instruction Set Attribute Register 1
p15, #0, r0, c0, c2, #2	ID_ISAR2	Instruction Set Attribute Register 2
p15, #0, r0, c0, c2, #3	ID_ISAR3	Instruction Set Attribute Register 3
p15, #0, r0, c0, c2, #4	ID_ISAR4	Instruction Set Attribute Register 4
p15, #0, r0, c0, c2, #5	ID_ISAR5	Instruction Set Attribute Register 5
p15, #1, r0, c0, c0, #0	CCSIDR	Cache Size ID Register
p15, #1, r0, c0, c0, #1	CLIDR	Cache Level ID Register
p15, #1, r0, c0, c0, #7	AIDR	Auxiliary ID Register
p15, #2, r0, c0, c0, #0	CSSELR	Cache Size Selection Register
p15, #0, r0, c1, c0, #0	SCTLR	System Control Register
p15, #0, r0, c1, c0, #1	ACTLR	Auxiliary Control Register
p15, #0, r0, c1, c0, #2	CPACR	Coprocessor Access Control Register
p15, #0, r0, c1, c1, #0	SCR	Secure Configuration Register
p15, #0, r0, c1, c1, #1	SDER	Secure Debug Enable Register
p15, #0, r0, c1, c1, #2	NSACR	Non-Secure Access Control Register
p15, #0, r0, c2, c0, #0	TTBR0	Translation Table Base Register 0
p15, #0, r0, c2, c0, #1	TTBR1	Translation Table Base Register 1
p15, #0, r0, c2, c0, #2	TTBCR	Translation Table Base Control Register
p15, #0, r0, c3, c0, #0	DACR	Domain Access Control Register
p15, #0, r0, c3, c0, #1	DACR	Undocumented. Write-Only. Used by ScePower.
p15, #0, r0, c3, c0, #2	DACR	Undocumented. Used by ScePower.
p15, #0, r0, c5, c0, #0	DFSR	Data Fault Status Register
p15, #0, r0, c5, c0, #1	IFSR	Instruction Fault Status Register
p15, #0, r0, c5, c1, #0	ADFSR	Auxiliary Data Fault Status Register
p15, #0, r0, c5, c1, #1	AIFSR	Auxiliary Instruction Fault Status Register
p15, #0, r0, c6, c0, #0	DFAR	Data Fault Address Register
p15, #0, r0, c6, c0, #2	IFAR	Instruction Fault Address Register
p15, #0, r0, c13, c0, #3	TPIDRURO	User Read-Only Thread ID Register. Value is TLS pointer.
p15, #0, r0, c13, c0, #4	TPIDRPRW	PL1 only Thread ID Register. Value is SceKernelThreadObject pointer.

Each core includes the following features:

• L1 Instruction Cache of 32 KiB and Data Cache of 32 KiB
• Media Processing Engine (MPE) that can execute Advanced SIMD instructions (NEONv1) and Vector Floating-Point v3 instructions (VFPv3)

In addition, there is a L2 cache of 2 MiB shared by all cores, while precisely speaking, it's external to the ARM processor core.

Documentation

A lot of useful information is available about ARM (Advanced RISC Machines) on the internet including ARM Ltd. official site.

• Refer to the following document for the instruction set, memory model and programmers' model: ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition.

• The ARM Cortex-A9 Technical Reference Manual gives a good overview of the specific processor features and is a good reference for what ARMv7 implementation specific features are enabled.

• Another manual that's important is the ARM Cortex-A9 MPCore Technical Reference Manual which is specific to the multi-core system the Vita uses. The main information of use are descriptors for the private memory region defined with the PERIPHBASE signal. This is mapped to physical address 0x1A000000.

• Cortex-A9 Technical Reference Manual

(corresponding to the chip revision supposed to be included in DevKit):

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0388f/DDI0388F_cortex_a9_r2p2_trm.pdf

• Cortex-A9 NEON Media Processing Engine Technical Reference Manual

(NEON: Advanced SIMD instructions)

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0409f/DDI0409F_cortex_a9_neon_mpe_r2p2_trm.pdf

• Cortex-A9 NEON MPE > VFPv3 architecture hardware support

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0409f/CHDEEJDB.html

(The above reference destination has been confirmed as of June 26, 2014. Note that pages may have been subsequently moved or its contents modified.)

Identification registers

Register name	Value
AIDR	0x00000000
CCSIDR	0x701FE019
CLIDR	0x09200003
CTR	0x83338003
ID_AFR0	0x00000000
ID_DFR0	0x00010444
ID_ISAR0	0x00101111
ID_ISAR1	0x13112111
ID_ISAR2	0x21232041
ID_ISAR3	0x11112131
ID_ISAR4	0x00011142
ID_ISAR5	0x00000000
ID_MMFR0	0x00100103
ID_MMFR1	0x20000000
ID_MMFR2	0x01230000
ID_MMFR3	0x00102111
ID_PFR0	0x00001231
ID_PFR1	0x00000011
MIDR	0x412FC09A
MPIDR	0x80000003
REVIDR	0x412FC09A
TCMTR	0x00000000
TLBTR	0x00000402

Interrupt Controller

As part of the Cortex A9 MPcore, the Vita also implements the Generic Interrupt Controller Architecture. More information on interrupts can be found here.

L2 Cache

PSVita uses the PL310 r3p1-50rel0 L2 cache (Cache ID Register = 0x410000C7) that is mapped to paddr 0x1A002000.

RO registers

Register name	Value
Cache ID Register	0x410000c7
Cache Type Register	0x1e440440