Caches

PL310 L2 Cache

The Vita uses the PL310 r3p1-50rel0 L2 cache (Cache ID Register = 0x410000C7) is is mapped to 0x1A002000.

RO Registers values

Offset	Value	Name
0x000	0x410000C7	Cache ID Register
0x004	0x1E440440	Cache Type Register

Configured values

It seems NSKBL initializes the Tag Latency Control Register to <1, 1, 1> (writes 0 to the L2 register), and Tag Latency Control Register to <2, 4, 2> (writes 0x131 to the L2 register).

Offset	Value	Name
0x100	0x00000001	Control Register
0x104	0x60090001	Auxiliary Control Register
0x108	0x00000000	Tag RAM Latency Control Register
0x10C	0x00000131	Data RAM Latency Control Register

Auxiliary Control Register

Bit(s)	Value	Field name	Description
0	1	Full Line of Zero Enable	Full line of write zero behavior Enabled
16	1	Associativity	16-way
19:17	4	Way-size	128KB
29	1	Instruction prefetch enable	Instruction prefetching enabled
30	1	Early BRESP enable	Early BRESP enabled