Pervasive

This device controls the clocks of the system.

ARM Clocks

The clocks are controlled by two registers at 0xE3103000 (ScePervasiveBaseClk). Currently, it is unknown how the values are interpreted. However, 0xE3103000 (one word) takes values 0 to 16, and increases clock speed while 0xE3103004 (single byte) takes values 0 to 8 and decreases clock speed. It is likely related to a PLL multiply and divide function. The input clock signal comes from a P1P40167 clock synthesizer (found on the bottom of the board under the main SoC). It takes a 27MHz crystal and generates a 37MHz clock which feeds directly into the SoC's internal PLL.

The following are tests run to determine what the values of each register corresponds to. It appears that the maximum clock speed is 500MHz and the minimum clock speed is 16MHz.

0xE3103000	0xE3103004	Clock Speed (MHz)
0	0	37
0	1	35
0	2	32
0	3	29
0	4	27
0	5	24
0	6	22
0	7	19
0	8	16
1	0	37
1	1	35
1	2	32
1	3	30
1	4	27
1	5	24
1	6	22
1	7	19
1	8	16
2	0	37
2	1	35
2	2	32
2	3	30
2	4	27
2	5	24
2	6	22
2	7	19
2	8	16
3	0	79
3	1	74
3	2	69
3	3	63
3	4	58
3	5	53
3	6	48
3	7	43
3	8	37
4	0	107
4	1	100
4	2	93
4	3	86
4	4	79
4	5	72
4	6	65
4	7	58
4	8	51
5	0	162
5	1	152
5	2	142
5	3	131
5	4	121
5	5	110
5	6	100
5	7	90
5	8	79
6	0	218
6	1	204
6	2	190
6	3	176
6	4	163
6	5	148
6	6	135
6	7	121
6	8	107
7	0	329
7	1	308
7	2	287
7	3	266
7	4	246
7	5	225
7	6	204
7	7	183
7	8	162
8	0	439
8	1	411
8	2	384
8	3	356
8	4	329
8	5	301
8	6	273
8	7	246
8	8	218
9	0	494
9	1	463
9	2	432
9	3	401
9	4	370
9	5	339
9	6	308
9	7	277
9	8	245
10	0	328
10	1	308
10	2	287
10	3	266
10	4	245
10	5	225
10	6	204
10	7	183
10	8	162
11	0	37
11	1	35
11	2	32
11	3	30
11	4	27
11	5	24
11	6	22
11	7	19
11	8	16
12	0	121
12	1	113
12	2	105
12	3	97
12	4	90
12	5	82
12	6	74
12	7	66
12	8	58
13	0	245
13	1	230
13	2	214
13	3	199
13	4	183
13	5	168
13	6	152
13	7	136
13	8	121
14	0	439
14	1	412
14	2	384
14	3	356
14	4	329
14	5	301
14	6	273
14	7	246
14	8	218
15	0	494
15	1	463
15	2	433
15	3	401
15	4	370
15	5	339
15	6	308
15	7	277
15	8	245
16	0	37
16	1	35
16	2	32
16	3	29
16	4	27
16	5	24
16	6	22
16	7	19
16	8	16

Clock Gating

Individual devices can be clock gated to preserve battery. To request the clock for a device to be enabled, do *REG32(0xE3102000 + dev_off) |= mask and to request the clock to be turned off do *REG32(0xE3102000 + dev_off) &= ~mask.

Reset

Devices must be put out of reset before they are first used. To put a device out of reset, do *REG32(0xE3101000 + dev_off) &= ~mask. To put a device in reset, do *REG32(0xE3101000 + dev_off) |= mask.

Misc

Devices can be fully disabled? by writing a 1 to the corresponding bit of the ScePervasiveMisc (PA 0xE3100000) register. To disable the device dev_off, do *REG32(0xE3100000 + (dev_off / 32) * 4) = 1 << (31 - (dev_off % 32)).

Pervasive2 (0xE3110000)

Offset	Description
0xF40	Bit 0 = Memory Card insert state

Devices

The offsets and masks are documented below. Some devices appear to only be accessible in secure world.

Offset	Description	Gate Mask	Reset Mask
16	? GpuEs4 related (Secure)	0xF00F
32	GPU	0xF000F
32	? (Secure)	0x3	0x3
36	? (Secure)	0x1	0x1
40	? GpuEs4 related (Secure)	0x1	0x1
48	Venezia	0x1	0x1
48	? (Secure)	0x2	0x2
52	Venezia related	0x1
64	Bus? (Secure)	0x1	0x1
68	? (Secure)	0x1	0x1
80	? (Secure)	0x1	0x1
84	? (Secure)	0x1	0x1
88	? (Secure)	0x1	0x1
92	? (Secure)	0x1	0x1
96	? (Secure)	0x1	0x1
100	? (Secure)	0x1	0x1
112	CSI0	0x1
116	CSI1	0x1
128	IFTU0	0xF	0x7
132	IFTU1	0xF	0x7
136	IFTU2	0xF	0x7
140	?	0x1
144	UDC0	0xA	0xA
148	UDC1	0xA	0xA
160	SDIF0	0x1
164	SDIF1	0x1
168	SDIF2	0x1
176	MSIF	0x1
192	I2s0 (Audio)	0x1	0x1
196	I2s1 (Audio)	0x1	0x1
200	I2s2 (Audio)	0x1	0x1
204	I2s3 (Audio)	0x1	0x1
208	I2s4 (Audio)	0x1	0x1
212	I2s5 (Audio)	0x1	0x1
216	I2s6 (Audio)	0x1	0x1
220	I2s7 (Audio)	0x1	0x1
224	SrcMix0 (Audio)	0x1	0x1
228	SrcMix1 (Audio)	0x1	0x1
232	SrcMix2 (Audio)	0x1	0x1
236
240	SPDIF (Audio)	0x1	0x1
256	GPIO	0x1	0x1
260	SPI0 (Syscon)	0x1	0x1
264	SPI1 (Motion)	0x1	0x1
268	SPI2 (OLED)	0x1	0x1
272	I2C0	0x1	0x1
276	I2C1	0x1	0x1
280
284
288	UART0 (Console)	0x1	0x1
292	UART1	0x1	0x1
296	UART2	0x1	0x1
300	UART3	0x1	0x1
304	UART4	0x1	0x1
308	UART5	0x1	0x1
312	UART6	0x1	0x1
356	LPDDR2	0x1	0x1
384	?		0x1