DSI Registers: Difference between revisions
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| Line 42: | Line 42: | ||
| 4 | | 4 | ||
| Interrupt enable mask (bit 1 = some interrupt) | | Interrupt enable mask (bit 1 = some interrupt) | ||
|- | |||
| 0x410 | |||
| 4 | |||
| DSI Command read FIFO status (bit 5 = Read FIFO empty) | |||
|- | |||
| 0x430 | |||
| 4 | |||
| DSI Command read FIFO | |||
|- | |- | ||
| 0x500 | | 0x500 | ||
| Line 49: | Line 57: | ||
| 0x510 | | 0x510 | ||
| 4 | | 4 | ||
| Another command FIFO | | Another command FIFO (used to write the packet for command reads) | ||
|- | |- | ||
| 0x838 | | 0x838 | ||
Revision as of 18:00, 9 February 2018
MMIO Interfaces
| Name | Physical address |
|---|---|
| SceDsi0Reg | 0xE5050000 |
| SceDsi1Reg | 0xE5060000 |
Registers
| Offset | Size | Description |
|---|---|---|
| 0x004 | 4 | bits 1:0: Video mode (0 = Progressive, 0b11 = Interlaced) |
| 0x00C | 4 | Clock related |
| 0x014 | 4 | Interrupts (read = triggered interrupts, write = clear interrupt) |
| 0x030 | 4 | bits[31:16] = VSW |
| 0x050 | 4 | Interrupt ack/clear |
| 0x054 | 4 | Interrupt enable mask (bit 1 = some interrupt) |
| 0x410 | 4 | DSI Command read FIFO status (bit 5 = Read FIFO empty) |
| 0x430 | 4 | DSI Command read FIFO |
| 0x500 | 4 | DSI Command FIFO |
| 0x510 | 4 | Another command FIFO (used to write the packet for command reads) |
| 0x838 | 4 | DSI auto clock configuration (1 = only HS clock, 0 = auto gate when data in LP) |