MMIO Interfaces
It looks like there are 7 UART devices/ports. The i-th device has its base registers address at SceUartReg + i * 0x10000.
The clock generator configuration for each of these devices is at SceUartClkgenReg + i * 4.
SceUartReg registers
| Offset
|
Size
|
Description
|
| 0x04
|
4
|
Enable device (1 = enable, 0 = disable)
|
| 0x10
|
4
|
??
|
| 0x20
|
4
|
??
|
| 0x28
|
4
|
Device status
|
| 0x30
|
4
|
??
|
| 0x40
|
4
|
?? A 0 is written here
|
| 0x50
|
4
|
??
|
| 0x54
|
4
|
A 0x77F is written here after reading from the FIFO
|
| 0x60
|
4
|
??
|
| 0x64
|
4
|
?? A 0x10001 is written here
|
| 0x68
|
4
|
Read FIFO data available
|
| 0x70
|
4
|
Write FIFO
|
| 0x78
|
4
|
Read FIFO
|
Device status
| Bit(s)
|
Description
|
| 8
|
Write FIFO not full (0 = full)
|
| 9
|
Device ready (0 = busy)
|
Read FIFO data available
| Bit(s)
|
Description
|
| 0-5
|
Number of words available to read
|
| 6-31
|
Unused
|
SceUartClkgenReg registers
| Offset
|
Size
|
Description
|
| 0x00
|
4
|
Clock generator for device 0
|
| 0x04
|
4
|
Clock generator for device 1
|
| 0x08
|
4
|
Clock generator for device 2
|
| 0x0C
|
4
|
Clock generator for device 3
|
| 0x10
|
4
|
Clock generator for device 4
|
| 0x14
|
4
|
Clock generator for device 5
|
| 0x18
|
4
|
Clock generator for device 6
|