Pervasive

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This device controls the clocks of the system.

ARM Clocks

The clocks are controlled by two registers at 0xE3103000 (ScePervasiveBaseClk). Currently, it is unknown how the values are interpreted. However, 0xE3103000 (one word) takes values 0 to 16, and increases clock speed while 0xE3103004 (single byte) takes values 0 to 8 and decreases clock speed. It is likely related to a PLL multiply and divide function. The input clock signal comes from a P1P40167 clock synthesizer (found on the bottom of the board under the main SoC). It takes a 27MHz crystal and generates a 37MHz clock which feeds directly into the SoC's internal PLL.

Register Device Note
0xE3103000 / 0xE3103004 CPU N/A
0xE3103010 Unknown N/A
0xE3103020 Unknown N/A
0xE3103030 Unknown N/A
0xE3103040 Unknown Set 0x60001 by second_loader
0xE3103044 Unknown N/A
0xE3103050 Unknown Set 1 by second_loader
0xE31030B0 Msif N/A
0xE3103124 Unknown N/A
0xE31031A4 Unknown N/A

The following are tests run to determine what the values of each register corresponds to. It appears that the maximum clock speed is 499MHz and the minimum clock speed is 16MHz.

These clocks may be wrong. Just "Kernel Clock Speed" is "Clock Speed + 5". However, there is an error of ± 5 to 6 in "Clock Speed".

0xE3103000 0xE3103004 Clock Speed (MHz) Kernel Clock Speed (MHz)
0 0 37 42
0 1 35 40
0 2 32 37
0 3 29 34
0 4 27 32
0 5 24 29
0 6 22 27
0 7 19 24
0 8 16 21
1 0 37 42
1 1 35 40
1 2 32 37
1 3 30 35
1 4 27 32
1 5 24 29
1 6 22 27
1 7 19 24
1 8 16 21
2 0 37 42
2 1 35 40
2 2 32 37
2 3 30 35
2 4 27 32
2 5 24 29
2 6 22 27
2 7 19 24
2 8 16 21
3 0 79 84
3 1 74 79
3 2 69 74
3 3 63 68
3 4 58 63
3 5 53 58
3 6 48 53
3 7 43 48
3 8 37 42
4 0 107 112
4 1 100 105
4 2 93 98
4 3 86 91
4 4 79 84
4 5 72 77
4 6 65 70
4 7 58 63
4 8 51 56
5 0 162 167
5 1 152 157
5 2 142 147
5 3 131 136
5 4 121 126
5 5 110 115
5 6 100 105
5 7 90 95
5 8 79 84
6 0 218 223
6 1 204 209
6 2 190 195
6 3 176 181
6 4 163 168
6 5 148 153
6 6 135 140
6 7 121 126
6 8 107 112
7 0 329 334
7 1 308 313
7 2 287 292
7 3 266 271
7 4 246 251
7 5 225 230
7 6 204 209
7 7 183 188
7 8 162 167
8 0 439 444
8 1 411 416
8 2 384 389
8 3 356 361
8 4 329 334
8 5 301 306
8 6 273 278
8 7 246 251
8 8 218 223
9 0 494 499
9 1 463 468
9 2 432 437
9 3 401 406
9 4 370 375
9 5 339 344
9 6 308 313
9 7 277 282
9 8 245 250
10 0 328 333
10 1 308 313
10 2 287 292
10 3 266 271
10 4 245 250
10 5 225 230
10 6 204 209
10 7 183 188
10 8 162 167
11 0 37 42
11 1 35 40
11 2 32 37
11 3 30 35
11 4 27 32
11 5 24 29
11 6 22 27
11 7 19 24
11 8 16 21
12 0 121 126
12 1 113 118
12 2 105 110
12 3 97 102
12 4 90 95
12 5 82 87
12 6 74 79
12 7 66 71
12 8 58 63
13 0 245 250
13 1 230 235
13 2 214 219
13 3 199 204
13 4 183 188
13 5 168 173
13 6 152 157
13 7 136 141
13 8 121 126
14 0 439 444
14 1 412 417
14 2 384 389
14 3 356 361
14 4 329 334
14 5 301 306
14 6 273 278
14 7 246 251
14 8 218 223
15 0 494 499
15 1 463 468
15 2 433 438
15 3 401 406
15 4 370 375
15 5 339 344
15 6 308 313
15 7 277 282
15 8 245 250
16 0 37 42
16 1 35 40
16 2 32 37
16 3 29 34
16 4 27 32
16 5 24 29
16 6 22 27
16 7 19 24
16 8 16 21

Clock Gating

Individual devices can be clock gated to preserve battery. To request the clock for a device to be enabled, do *REG32(0xE3102000 + dev_off) |= mask and to request the clock to be turned off do *REG32(0xE3102000 + dev_off) &= ~mask.

Reset

Devices must be put out of reset before they are first used. To put a device out of reset, do *REG32(0xE3101000 + dev_off) &= ~mask. To put a device in reset, do *REG32(0xE3101000 + dev_off) |= mask.

Misc

Devices can be fully disabled? by writing a 1 to the corresponding bit of the ScePervasiveMisc (PA 0xE3100000) register. To disable the device dev_off, do *REG32(0xE3100000 + (dev_off / 32) * 4) = 1 << (31 - (dev_off % 32)).

ScePervasiveMisc (0xE3100000)

Offset Description
0x0000 SoC revision. ex:0x80000115
0x0004 Unknown

Pervasive2 (0xE3110000)

Offset Description
0xF40 Bit 0 = Memory Card insert state

Devices

The offsets and masks are documented below. Some devices appear to only be accessible in secure world.

Offset Description Gate Mask Reset Mask
16 ? GpuEs4 related (Secure) 0xF00F
32 GPU 0xF000F
32 ? (Secure) 0x3 0x3
36 ? (Secure) 0x1 0x1
40 ? GpuEs4 and SceEmcTop related (Secure) 0x1 0x1
48 Venezia 0x1 0x1
48 ? (Secure) 0x2 0x2
52 Venezia related 0x1
64 Bus? (Secure) 0x1 0x1
68 ? (Secure) 0x1 0x1
80 ? (Secure) 0x1 0x1
84 ? (Secure) 0x1 0x1
88 ? (Secure) 0x1 0x1
92 ? (Secure) 0x1 0x1
96 ? (Secure) 0x1 0x1
100 ? (Secure) 0x1 0x1
112 CSI0 0x1
116 CSI1 0x1
128 IFTU0 0xF 0x7
132 IFTU1 0xF 0x7
136 IFTU2 0xF 0x7
140 ? 0x1
144 UDC0 0xA 0xA
148 UDC1 0xA 0xA
160 SDIF0 0x1
164 SDIF1 0x1
168 SDIF2 0x1
176 MSIF 0x1
192 I2s0 (Audio) 0x1 0x1
196 I2s1 (Audio) 0x1 0x1
200 I2s2 (Audio) 0x1 0x1
204 I2s3 (Audio) 0x1 0x1
208 I2s4 (Audio) 0x1 0x1
212 I2s5 (Audio) 0x1 0x1
216 I2s6 (Audio) 0x1 0x1
220 I2s7 (Audio) 0x1 0x1
224 SrcMix0 (Audio) 0x1 0x1
228 SrcMix1 (Audio) 0x1 0x1
232 SrcMix2 (Audio) 0x1 0x1
236
240 SPDIF (Audio) 0x1 0x1
256 GPIO 0x1 0x1
260 SPI0 (Syscon) 0x1 0x1
264 SPI1 (Motion) 0x1 0x1
268 SPI2 (OLED) 0x1 0x1
272 I2C0 0x1 0x1
276 I2C1 0x1 0x1
280
284
288 UART0 (Console) 0x1 0x1
292 UART1 0x1 0x1
296 UART2 0x1 0x1
300 UART3 0x1 0x1
304 UART4 0x1 0x1
308 UART5 0x1 0x1
312 UART6 0x1 0x1
352 LPDDR2MAIN 0x1 0x1
356 LPDDR2SUB 0x1 0x1
384 ? 0x1
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