Cortex A9 MPcore
The custom SoC includes the ARM Cortex-A9 MPCore as its CPU, mounting four little-endian ARM Cortex-A9 processor cores, which is common in modern high performance embedded devices like cell phones and tablets. The PSVita cores have a MIDR value of
0x412FC09A, meaning it is Cortex-A9 r2p10. Indeed there are usage of undocumented CP15 registers.
Each core includes the following features:
- L1 Instruction Cache of 32 KiB and Data Cache of 32 KiB
- Media Processing Engine (MPE) that can execute Advanced SIMD instructions (NEONv1) and Vector Floating-Point v3 instructions (VFPv3)
In addition, there is a L2 cache of 2 MiB shared by all cores, while precisely speaking, it's external to the ARM processor core.
A lot of useful information is available about ARM (Advanced RISC Machines) on the internet including ARM Ltd. official site.
- Refer to the following document for the instruction set, memory model and programmers' model: ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition.
- The ARM Cortex-A9 Technical Reference Manual gives a good overview of the specific processor features and is a good reference for what ARMv7 implementation specific features are enabled.
- Another manual that's important is the ARM Cortex-A9 MPCore Technical Reference Manual which is specific to the multi-core system the Vita uses. The main information of use are descriptors for the private memory region defined with the
PERIPHBASEsignal. This is mapped to physical address
- Cortex-A9 Technical Reference Manual
(corresponding to the chip revision supposed to be included in DevKit):
- Cortex-A9 NEON Media Processing Engine Technical Reference Manual
(NEON: Advanced SIMD instructions)
- Cortex-A9 NEON MPE > VFPv3 architecture hardware support
(The above reference destination has been confirmed as of June 26, 2014. Note that pages may have been subsequently moved or its contents modified.)
|Cache ID Register||0x410000c7|
|Cache Type Register||0x1e440440|