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no edit summary
| 0x8000
| 0x8000
| S
| S
| Alias of <code>0x1F000000</code>, ScePower scratch buffer
| ARM Boot. Alias of <code>0x1F000000</code>, ScePower scratch buffer
|-
|-
| 0x00040000
| 0x00040000
| 0x20000
| 0x20000
| S
| S
| Mirror of 0x00800000.
| MeP boot. Mirror of 0x00800000.
|-
|-
| 0x00300000
| 0x00300000
| 0x10000
| 0x10000
| S
| S
| F00D icache
| cmep icache
|-
|-
| 0x00310000
| 0x00310000
| 0x10000
| 0x10000
| S
| S
| F00D icache tag
| cmep icache tag
|-
|-
| 0x00320000
| 0x00320000
| 0x10000
| 0x10000
| S
| S
| F00D dcache
| cmep dcache
|-
|-
| 0x00330000
| 0x00330000
| 0x10000
| 0x10000
| S
| S
| F00D dcache tag
| cmep dcache tag
|-
| 0x004B0000
| 0x005FFFFF
| 0x150000
| S
| Reverved for Venezia
|-
| 0x00600000
| 0x007FFFFF
| 0x200000
| S
| Reserved for MeP
|-
|-
| 0x00800000
| 0x00800000
| 0x20000
| 0x20000
| S
| S
| F00D private 128KiB SRAM. [[Secure_Kernel|secure kernel]], [[Sm_modules|sm location]]
| cMeP 128KiB SRAM. [[Secure_Kernel|secure kernel]], [[Sm_modules|sm location]]. Mirror of SPAD128K ?
|-
|-
| 0x1A000000
| 0x1A000000
| 0x2000
| 0x2000
| NS/S
| NS/S
| SceInterruptControllerReg / ScePeriphReg, [[Interrupts]] (<code>PERIPHBASE</code>)
| ARM, SceInterruptControllerReg / ScePeriphReg, [[Interrupts]] (<code>PERIPHBASE</code>)
|-
|-
| 0x1A002000
| 0x1A002000
| 0x1000
| 0x1000
| NS/S
| NS/S
| ScePl310Reg / SceL2CacheReg, [[L2 Cache Controller]]
| ARM. ScePl310Reg / SceL2CacheReg, [[L2 Cache Controller]]
|-
|-
| 0x1C000000
| 0x1C000000
| 0x200000
| 0x200000
| NS/S
| NS/S
| SceDisplay / SceCameraSRAM (only 960x544 pixels * 4 bytes = 0x1FE000 bytes mapped)
| Tachyon-eDRAM. SceDisplay / SceCamera SRAM (only 960x544 pixels * 4 bytes = 0x1FE000 bytes mapped)
|-
|-
| 0x1F000000
| 0x1F000000
| 0x8000
| 0x8000
| NS/S
| NS/S
| ScePowerScratchPad32KiB
| SPAD32K. ScePowerScratchPad32KiB
|-
|-
| 0x1F840000
| 0x1F840000
| 0x20000
| 0x20000
| NS/S
| NS/S
| [[Venezia|SceVeneziaSpram]] - Stores Secure Kernel on boot
| SPAD128K. [[Venezia|SceVeneziaSpram]]. Stores Secure Kernel on boot.
|-
|-
| 0x20000000
| 0x20000000
| 0x8000000
| 0x8000000
| NS
| NS
| [[VRAM]]
| [[VRAM]]. Graphics bar
|-
|-
| 0x30000000
| 0x30000000
| 0x20000000
| 0x20000000
| NS/S
| NS/S
| Maybe not used.
| Reserved for Venezia. Maybe unused.
|-
|-
| 0xE0000000
| 0xE0000000
| 0x100000
| 0x100000
| S
| S
| [[#F00D Processor|F00D Processor]]
| Control Register. [[#cmep|cmep]]
|-
|-
| 0xE0100000
| 0xE0100000
| 0x1000
| 0x1000
| S
| S
| Cortex A9 Debug ROM Table
| ARM Cortex-A9 Debug ROM Table
|-
|-
| 0xE3310000
| 0xE3310000
| 0x4000
| 0x4000
| NS
| NS
| SceIntrmgrVfpIntRegs
| ARM-VFP. SceIntrmgrVfpIntRegs
|-
|-
| 0xE4020000
| 0xE4020000
| 0x1000
| 0x1000
| NS
| NS
| SceUsbdEhci
| USB2_OHCI. SceUsbdEhci
|-
|-
| 0xE40B0000
| 0xE40B0000
| 0x2000
| 0x2000
| S
| S
| SceSonyRegbus
| SceSonyRegbus. GPU Control
|-
|-
| 0xE8100000
| 0xE8100000
| ?
| ?
| ?
| ?
| Mapped by SKBL. May be related to F00D reset.
| Mapped by SKBL. Maybe related to cmep reset.
|-
|-
| 0xED000000
| 0xED000000
| ?
| ?
| Mapped by SKBL
| Mapped by SKBL
|-
| 0xF0000000
| ?
| ?
| ?
| Reserved for Venezia
|}
|}
Notes:
Notes:
*The first 0xC0 bytes of the Text segment are the reset vector.
* The first 0xC0 bytes of the Text segment are the reset vector.
* NSKBL is mapped in RWX mode so it may write itself to text segment.
* NSKBL is mapped in RWX mode so it may write itself to text segment.
== F00D Processor ==
== cmep ==
Each F00D device has its own physical memory area.
Each cmep device has its own physical memory area.
{| class='wikitable'
{| class='wikitable'
| 0xE0010000
| 0xE0010000
| 0xE001FFFF
| 0xE001FFFF
| F00D Reset
| cmep Reset
|-
|-
| 0xE0020000
| 0xE0020000