SceExcpmgr

SceExcpmgr is a kernel module that sets up exception handling. A version exists in both worlds. In non-secure world, after the kernel is booted up, the exception handlers pointed to by VBAR all jump into code in this module.

Module
This module exists in both non-secure and secure world. The non-secure world SELF can be found in.

Libraries
This module only exports kernel libraries.

To find
sceKernelDefaultHandlerCfunc sceKernelDefaultHandlerSvcCfunc sceKernelDefaultHandlerIrqCfunc sceKernelDefaultHandlerReservedCfunc sceKernelPanicHandlerUndefCfunc sceKernelPanicHandlerDabtCfunc sceKernelPanicHandlerPabtCfunc

These 7 function names must be of the following NIDs:

sceExcpmgrGetDataForKernel: 0x08CB30E6 SceExcpmgrForKernel_3AE9AEE1: 0x3AE9AEE1 SceExcpmgrForKernel_4FF90618: 0x4FF90618 SceExcpmgrForKernel_7ADF11DB: 0x7ADF11DB SceExcpmgrForKernel_8D223205: 0x8D223205 SceExcpmgrForKernel_A66DDFA3: 0xA66DDFA3 SceExcpmgrForKernel_C45C0D3D: 0xC45C0D3D SceExcpmgrForKernel_D464A9A7: 0xD464A9A7

sceKernelRegisterExceptionHandlerForKernel
Temp name was sceExcpmgrRegisterHandlerForKernel.

Installs an exception handler.

The function must be ARM and not thumb, and the allowed priority values are from 0 to 7 (including them).

Where excpcode can be:
 * Reset (RESET): 0
 * Undefined Instruction (UNDEF): 1
 * Supervisor Call (SVC): 2
 * Prefetch Abort (PABT): 3
 * Data Abort (DABT): 4
 * Reserved (RESERVED): 5
 * Interrupt (IRQ): 6
 * Fast Interrupt (FIQ): 7

The syscall handler in FW 1.50 is SceExcpmgr_func_0x81000E40.

SVC
SVC (Supervisor Call), more commonly called Syscalls (system calls), is what allows to interact with non-secure kernel from usermode.

The SVC interface is defined in non-secure kernel as:

On return, R1-R3 and R12 are cleared to 0x0 or 0xDEADBEEF to prevent any data leaks. All user pointers passed to syscalls are accessed with ARM instructions LDRT and STRT for hardware forced permission checks. Syscalls 0x0 - 0xFF are likely a "fastcall" interface that do not mask interrupts or set the DACR, however currently are no such fastcalls defined. Syscalls 0x100 - 0xFFF are made with IRQ interrupts masked and DACR set to 0xFFFF0000 (to prevent access to certain memory domains). Any other syscall numbers are invalid.

System calls are handled in "system" mode defined in ARMv7 (mode 0b11111).

User exported functions loaded by SceKernelModulemgr are exported as syscalls. The number assigned to the syscall are randomized with respect to each library but not within a library. That means, for example, two functions exported by a library will always be some syscall number apart even though that number will change on each boot.

There is no SVC in secure world because all code in secure world is running as kernel.

SMC
SMC (Secure Monitor Call) is what allows to interact with ARM TrustZone from non-secure kernel.

The SMC interface for making a non-secure kernel call to secure kernel is:

The SMC interface is very similar to SVC interface. The SMC handler and MVBAR is set up in Secure World by SceExcpmgrForTZS.

0x0 - 0xFF are fast service calls. 0x100 - 0xFFF are normal service calls ran with IRQs masked.

Secure services are ran in ARM system processor mode (0b11111) in the Secure World.

SMC calls are registered by SceIntrmgrForTZS functions.

Aborts
On development units, data and prefetch aborts can handle BKPT instruction for software breakpoints. SceDebug uses this to handle usermode breakpoints. There is no built-in support for BKPT in kernel code.

SceSysmem uses data aborts with the  and   instructions to implement user pointer checking. When LDRT/STRT throws a MMU data exception because of an invalid access and the exception came from SceSysmem or SceSysmem or related functions, the data abort handler will resume execution.

IRQ
IRQs are only handled in non-secure world. An IRQ in secure world is fatal. See SceKernelIntrMgr.

FIQ
FIQs are only handled in secure world because of the bit set in the SCR. Because of this, it is likely that secure devices such as the F00D Processor use FIQs to communicate with the Cortex A9 cores. See SceKernelIntrMgr.