SceKernelIntrMgr

SceKernelIntrMgr is a kernel module that is primary responsible for setting up external and internal interrupts. Notably, it facilitates communication with the F00D Processor.

Module
This module exists in both non-secure and secure world. The non-secure world SELF can be found in. It also can be found in the Boot Image.

Libraries
This module only exports kernel libraries.

Remove interrupt handler
This function first performs a clear-enable and then removes the current interrupt handler associated with the interrupt.

Clear-enable interrupt
This function writes  to the Interrupt Clear-Enable register (offset 0x180 from the Interrupt Distributor registers) at

Controller
The interrupt controller is defined in the MPCore TRM. The PERIPHBASE address (physical) is 0x1A000000.

Registered Interrupts
As specified in GIC Architecture, interrupt 0-15 are software generated interrupts. There are also no private peripheral interrupts (16-31) implemented. Core Handler indicates which core handles the exception. "All" means it can be handled by any core.