SGX543

General Info
It looks like instructions are 8 bytes long. Roughly speaking - first 4 bytes contain opcode and addressing mode. Second 4 bytes contain operands encoding.

Bit encoding used in this reference:

Predicates
Not sure about predicates yet, but they are used to mask execution of certain instructions.

Notation is the following:

For example:

To reduce amount of examples - they are not listed with predicates.

It is assumed that all predicates are applicable to all instructions in the group unless opposite is indicated.

Operands
Currently - only known form of operands is registers.

Instructions may have up to four operands specified.

In this documentation they will be encoded as:

Registers

 * pa - primary attribute register. 32 bit long.
 * sa - secondary attribute register. 32 bit long.
 * o - output register. 32 bit long.
 * r - temporary register. 32 bit long.
 * i - internal register. 128 bit long.

Register Selector RS2
This encoding uses 2 bits to encode register type.

selector is encoded as:

Note that internal registers are not encoded - they are reserved in Register R6

Register Selector Indexable RSI2
This encoding uses 2 bits to encode register type.

selector is encoded as:

When index mode is used - there has to be another field that encodes index expression with Register Index Offset RIO6

The way that index expression is buit:

Example:

Register R6
This encoding uses 6 bits to encode register index.

register is encoded as:

index is calculated as: value * 2

Register expression is built as:

Example:

Specific type of register can be selected with Register Selector RS2

For destination operand op0 specific type of register can be selected with Register Selector Indexable RSI2

Last 4 values are reserved for internal registers i0, i1, i2, i3

Register RI2
This encoding uses 2 bits to encode internal register.

Register Index Offset RIO6
rt is encoded as Register Selector RS2

offset is calculated as: value * 2

offset is encoded as:

Register Swizzle RSWZ2
This encoding uses 2 bits to encode the mask.

channel is encoded as:

swizzle expression is built as:

Example:

Register Swizzle RSWZ3
This encoding uses 3 bits to encode the mask.

channel is encoded as:

swizzle expression is built as:

Example:

Immediate IMM6
Some operands may act as immediate values which are encoded using 6 bits.

Constant CNST6
Some operands may act as constant values which are encoded using 6 bits.

Constants are taken from table below.

Constants differ in 32 and 16 bit mode.

Table for 16 bit mode does not have accurate values.

Modifier and dest data format
At the moment it is not known which of the data format fields is dest and which is source.

This is the reason why term modifier is mixed with term dest data format.

Instructions
mad

Encoding
Higher 4 bytes

Lower 4 bytes

Fields (operands)

 * swz_alt_op1 - does not have effect on its own. can be used together with swz_mask32 or swz_mask16 to change op1 swizzle. does not have effect with swz_en.

when both swz_mask32 or swz_mask16 and swz_en are enabled - changes op1 swizzle differently.


 * alt_opt0 - alter opt0. this bit can be combined with opt0 to produce the following modes for op0:
 * abs_op1 - add abs modifier to op1. example:
 * alt_opt2 - alter opt2. this bit can be combined with opt2 to produce the following modes for op2:
 * alt_opt3 - alter opt3. this bit can be combined with opt3 to produce the following modes for op3:
 * swz_alt_op3 - does not have effect on its own. can be used together with swz_mask32 or swz_mask16 to change op3 swizzle. does not have effect with swz_en.

when both swz_mask32 or swz_mask16 and swz_en are enabled - changes op3 swizzle differently.


 * op3_swz - op3 swizzle encoded with Register Swizzle RSWZ2. does not have effect on its own. must be used with swz_en or swz_mask32 or swz_mask16 or both.
 * swz_alt_op2 - does not have effect on its own. can be used together with swz_mask32 or swz_mask16 to change op2 swizzle. does not have effect with swz_en.

when both swz_mask32 or swz_mask16 and swz_en are enabled - changes op2 swizzle differently.

or with Register Index Offset RIO6 using index2 mode if specified in alt_opt0. or with CNST6 if specified in alt_opt0. or with Register Index Offset RIO6 using index2 mode if specified in alt_opt2. or IMM6 if specified in alt_opt2. or with CNST6 if specified in alt_opt2. or with Register Index Offset RIO6 using index2 mode if specified in alt_opt3. or IMM6 if specified in alt_opt3. or with CNST6 if specified in alt_opt3.
 * swz_mask16 - masks first two channels for swizzles that are controlled by op1_swz, op2_swz, op3_swz. applies only to mad.f16
 * swz_mask32 - masks first channel for swizzles that are controlled by op1_swz, op2_swz, op3_swz. applies only to mad.f32
 * swz_en - enables usage of swizzling that is controlled by op1_swz, op2_swz, op3_swz. swizzle of op0 can be changed only with swz_en or swz_mask32 or swz_mask16 and does not have dedicated field.
 * abs_op2 - add abs modifier to op2. example:
 * neg_op2 - negate op2. example:
 * abs_op3 - add abs modifier to op3. example:
 * neg_op3 - negate op3. example:
 * opt1 - when enabled - selects pa register type. when disabled - selects r register type.
 * opt0 - type of operand op0, encoded with Register Selector Indexable RSI2. or selects other modes for encoding op0 if specified in alt_opt0.
 * opt2 - type of operand op2, encoded with Register Selector RS2. or selects other modes for encoding op2 if specified in alt_opt2.
 * opt3 - type of operand op3, encoded with Register Selector RS2. or selects other modes for encoding op3 if specified in alt_opt3.
 * op0 - op0 encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in opt0.
 * op2_swz - op2 swizzle encoded with Register Swizzle RSWZ2. does not have effect on its own. must be used with swz_en or swz_mask32 or swz_mask16 or both.
 * op1_swz - op1 swizzle encoded with Register Swizzle RSWZ2. does not have effect on its own. must be used with swz_en or swz_mask32 or swz_mask16 or both.
 * op1 - encoded with Register R6
 * op2 - encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in alt_opt2.
 * op3 - encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in alt_opt3.

Constants
Specific operand may be used as float constant. This can be achieved with following groups of bits:


 * alt_opt0, opt0, op0
 * alt_opt2, opt2, op2
 * alt_opt3, opt3, op3

Float constants can only be used when swizzling is enabled for particular operand. Consider checking sections Swizzles_f32 and Swizzles_f16.

Constants are taken from tables Constants.

Constants differ between 32 and 16 bit mode.

Constants are same for each operand.

Swizzles f32
There are multiple combinations available, controlled by:
 * swizzle fields: op1_swz, op2_swz, op3_swz
 * control bits: swz_en, swz_mask32, swz_alt_op1, swz_alt_op2, swz_alt_op3

Swizzles of operand 0, operand 1 and operand 2 can not be precisely controlled and have predefined combinations:

Swizzles f16
There are multiple combinations available, controlled by:
 * swizzle fields: op1_swz, op2_swz, op3_swz
 * control bits: swz_en, swz_mask16, swz_alt_op1, swz_alt_op2, swz_alt_op3

Swizzles of operand 0, operand 1 and operand 2 can not be precisely controlled and have predefined combinations:

Instructions
mul.f32, add.f32, frc.f32, dsx.f32, dsy.f32, min.f32, max.f32, dot.f32

Encoding
Higher 4 bytes

Lower 4 bytes

Fields (operands)
or with Register Index Offset RIO6 using index2 mode if specified in alt_opt0. or with CNST6 if specified in alt_opt0. or with Register Index Offset RIO6 using index2 mode if specified in alt_opt1. or IMM6 if specified in alt_opt1. or with CNST6 if specified in alt_opt1. or with Register Index Offset RIO6 using index2 mode if specified in alt_opt2. or IMM6 if specified in alt_opt2. or with CNST6 if specified in alt_opt2.
 * op1_swz_c3x - operand 1 swizzling channel 3 bit 1, 2. encoded as RSWZ3.
 * alt_opt0 - alter opt0. this bit can be combined with opt0 to produce the following modes for op0:
 * op1_swz_c30 - operand 1 swizzling channel 3 bit 0. encoded as RSWZ3.
 * alt_opt1 - alter opt1. this bit can be combined with opt1 to produce the following modes for op1:
 * alt_opt2 - alter opt2. this bit can be combined with opt2 to produce the following modes for op2:
 * swz_alt_op2 - change op2 swizzle.
 * op2_swz - op2 swizzle encoded with Register Swizzle RSWZ2.
 * swz_mask3 - masks first, second and third channel for swizzles
 * swz_mask2 - masks first and second channel for swizzles
 * swz_mask1 - masks first channel for swizzles
 * swz_en - enables usage of swizzling.
 * abs_op1 - add abs modifier to op1.
 * neg_op1 - negate op1.
 * abs_op2 - add abs modifier to op2.
 * op1_swz_c2x - operand 1 swizzling channel 2 bit 1, 2. encoded as RSWZ3.
 * opt0 - type of operand op0, encoded with Register Selector Indexable RSI2. or selects other modes for encoding op0 if specified in alt_opt0.
 * opt1 - type of operand op1, encoded with Register Selector RS2. or selects other modes for encoding op1 if specified in alt_opt1.
 * opt2 - type of operand op2, encoded with Register Selector RS2. or selects other modes for encoding op2 if specified in alt_opt2.
 * op0 - op0 encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in opt0.
 * op1_swz_c20 - operand 1 swizzling channel 2 bit 0. encoded as RSWZ3.
 * op1_swz_c1 - operand 1 swizzling channel 1. encoded as RSWZ3.
 * op1_swz_c0 - operand 1 swizzling channel 0. encoded as RSWZ3.
 * op1 - encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in alt_opt1.
 * op2 - encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in alt_opt2.

Constants
Specific operand may be used as float constant. This can be achieved with following groups of bits:


 * alt_opt0, opt0, op0
 * alt_opt1, opt1, op1
 * alt_opt2, opt2, op2

Float constants can only be used when swizzling is enabled for particular operand. Consider checking sections Swizzle_masking.

Constants are taken from tables Constants.

Constants correspond to table for 32 bit mode.

Constants are same for each operand.

Swizzle notation
When some of channels have constants - text notation is used

When all channels have constants - constant notation is used

When channel is masked in text notation it is marked as

When channel is masked in constant notation it is replaced with zero

Swizzle masking
Masking is controled by control bits:
 * control bits: swz_en, swz_mask1, swz_mask2, swz_mask3

Each channel can be masked with control bits. Combinations of control bits produce the following masking table.

''dot.f32 instruction has explicit swizzling in operand 1 and operand 2 so masking does not apply to these operands. number of channels is always 3.''

Encoding used in masking table:

Masking table:

Swizzles (operand 0)
Swizzles of operand 0 can not be controled and have predefined combinations described below:

Each channel can be masked with control bits. Masking is described in Swizzle_masking.


 * swz_en, swz_mask1, swz_mask2, swz_mask3

Swizzles (operand 1)
Each channel of operand 1 can be precisely controlled with swizzle fields encoded as RSWZ3.


 * op1_swz_c0, op1_swz_c1, op1_swz_c20, op1_swz_c2x, op1_swz_c30, op1_swz_c3x

Each channel can be masked with control bits. Masking is described in Swizzle_masking.


 * swz_en, swz_mask1, swz_mask2, swz_mask3

masking does not apply for dot.f32 instruction

Swizzles (operand 2)
Swizzles of operand 2 can not be precisely controlled and have predefined combinations described below and controlled by swizzle fields:


 * op2_swz, swz_alt_op2

Each channel can be masked with control bits. Masking is described in Swizzle_masking.


 * swz_en, swz_mask1, swz_mask2, swz_mask3

masking does not apply for dot.f32 instruction

Instructions
mul.f16, add.f16, frc.f16, dsx.f16, dsy.f16, min.f16, max.f16, dot.f16

Encoding
Higher 4 bytes

Lower 4 bytes

Fields (operands)
or with Register Index Offset RIO6 using index2 mode if specified in alt_opt0. or with CNST6 if specified in alt_opt0. or with Register Index Offset RIO6 using index2 mode if specified in alt_opt1. or IMM6 if specified in alt_opt1. or with CNST6 if specified in alt_opt1. or with Register Index Offset RIO6 using index2 mode if specified in alt_opt2. or IMM6 if specified in alt_opt2. or with CNST6 if specified in alt_opt2.
 * op1_swz_c3x - operand 1 swizzling channel 3 bit 1, 2. encoded as RSWZ3.
 * alt_opt0 - alter opt0. this bit can be combined with opt0 to produce the following modes for op0:
 * op1_swz_c30 - operand 1 swizzling channel 3 bit 0. encoded as RSWZ3.
 * alt_opt1 - alter opt1. this bit can be combined with opt1 to produce the following modes for op1:
 * alt_opt2 - alter opt2. this bit can be combined with opt2 to produce the following modes for op2:
 * swz_alt_op2 - change op2 swizzle.
 * op2_swz - op2 swizzle encoded with Register Swizzle RSWZ2.
 * swz_mask3 - masks first, second and third channel for swizzles
 * swz_mask2 - masks first and second channel for swizzles
 * swz_mask1 - masks first channel for swizzles
 * swz_en - enables usage of swizzling.
 * abs_op1 - add abs modifier to op1.
 * neg_op1 - negate op1.
 * abs_op2 - add abs modifier to op2.
 * op1_swz_c2x - operand 1 swizzling channel 2 bit 1, 2. encoded as RSWZ3.
 * opt0 - type of operand op0, encoded with Register Selector Indexable RSI2. or selects other modes for encoding op0 if specified in alt_opt0.
 * opt1 - type of operand op1, encoded with Register Selector RS2. or selects other modes for encoding op1 if specified in alt_opt1.
 * opt2 - type of operand op2, encoded with Register Selector RS2. or selects other modes for encoding op2 if specified in alt_opt2.
 * op0 - op0 encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in opt0.
 * op1_swz_c20 - operand 1 swizzling channel 2 bit 0. encoded as RSWZ3.
 * op1_swz_c1 - operand 1 swizzling channel 1. encoded as RSWZ3.
 * op1_swz_c0 - operand 1 swizzling channel 0. encoded as RSWZ3.
 * op1 - encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in alt_opt1.
 * op2 - encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in alt_opt2.

Constants
Specific operand may be used as float constant. This can be achieved with following groups of bits:


 * alt_opt0, opt0, op0
 * alt_opt1, opt1, op1
 * alt_opt2, opt2, op2

Float constants can only be used when swizzling is enabled for particular operand. Consider checking sections Swizzle_masking.

Constants are taken from tables Constants.

Constants correspond to table for 16 bit mode.

Constants are same for each operand.

Swizzle notation
When some of channels have constants - text notation is used

When all channels have constants - constant notation is used

When channel is masked in text notation it is marked as

When channel is masked in constant notation it is replaced with zero

Swizzle masking
Masking is controled by control bits:
 * control bits: swz_en, swz_mask1, swz_mask2, swz_mask3

Each channel can be masked with control bits. Combinations of control bits produce the following masking table.

''dot.f16 instruction has explicit swizzling in operand 1 and operand 2 so masking does not apply to these operands. number of channels is always 3.''

Encoding used in masking table:

Masking table:

Swizzles (operand 0)
Swizzles of operand 0 can not be controled and have predefined combinations described below:

Each channel can be masked with control bits. Masking is described in Swizzle_masking.


 * swz_en, swz_mask1, swz_mask2, swz_mask3

Swizzles (operand 1)
Each channel of operand 1 can be precisely controlled with swizzle fields encoded as RSWZ3.


 * op1_swz_c0, op1_swz_c1, op1_swz_c20, op1_swz_c2x, op1_swz_c30, op1_swz_c3x

Each channel can be masked with control bits. Masking is described in Swizzle_masking.


 * swz_en, swz_mask1, swz_mask2, swz_mask3

masking does not apply for dot.f16 instruction

Swizzles (operand 2)
Swizzles of operand 2 can not be precisely controlled and have predefined combinations described below and controlled by swizzle fields:


 * op2_swz, swz_alt_op2

Each channel can be masked with control bits. Masking is described in Swizzle_masking.


 * swz_en, swz_mask1, swz_mask2, swz_mask3

masking does not apply for dot.f16 instruction

Instructions
dot.f32, mad.f32

Encoding (dot.f32)
Higher 4 bytes

Lower 4 bytes

Encoding (mad.f32)
Higher 4 bytes

Lower 4 bytes

Fields (operands) dot.f32

 * c3_en - enable channel 3 for swizzles for op1 and op2. by default dot.f32 has only 3 channels for op1 and op2.


 * alt_opt0 - alter opt0. this bit can be combined with opt0 to produce the following modes for op0:


 * alt_opt1 - alter opt1. this bit can be combined with opt1 to produce the following modes for op1:

or with Register Index Offset RIO6 using index2 mode if specified in alt_opt0. or with CNST6 if specified in alt_opt0. or with Register Index Offset RIO6 using index2 mode if specified in alt_opt1. or IMM6 if specified in alt_opt1. or with CNST6 if specified in alt_opt1.
 * abs_op2 - add abs modifier to op2.
 * swz_en_strange1 - force overrides swizzle masking with single channel
 * swz_en_strange0 - force overrides swizzle masking with single channel
 * swz_mask3 - masks first, second and third channel for swizzles
 * swz_mask2 - masks first and second channel for swizzles
 * swz_mask1 - masks first channel for swizzles
 * swz_en - enables usage of swizzling.
 * neg_op1 - negate op1.
 * abs_op1 - add abs modifier to op1.
 * opt0 - type of operand op0, encoded with Register Selector Indexable RSI2. or selects other modes for encoding op0 if specified in alt_opt0.
 * opt1 - type of operand op1, encoded with Register Selector RS2. or selects other modes for encoding op1 if specified in alt_opt1.
 * op2i - encoded with RI2
 * op0 - op0 encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in opt0.
 * swz_alt_op2 - change op2 swizzle.
 * op2_swz - op2 swizzle encoded with Register Swizzle RSWZ2.
 * op1_swz_c3 - operand 1 swizzling channel 3. encoded as RSWZ3.
 * op1_swz_c2 - operand 1 swizzling channel 2. encoded as RSWZ3.
 * op1_swz_c1 - operand 1 swizzling channel 1. encoded as RSWZ3.
 * op1_swz_c0 - operand 1 swizzling channel 0. encoded as RSWZ3.
 * op1 - encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in alt_opt1.

Constants
Specific operand may be used as float constant. This can be achieved with following groups of bits:


 * alt_opt0, opt0, op0
 * alt_opt1, opt1, op1

Float constants can only be used when swizzling is enabled for particular operand. Consider checking sections Swizzle_masking.

Constants are taken from tables Constants.

Constants correspond to table for 32 bit mode.

Constants are same for each operand.

Swizzle masking (dot.f32)
Masking is controled by control bits:
 * control bits: swz_en, swz_mask1, swz_mask2, swz_mask3

Each channel can be masked with control bits. Combinations of control bits produce the following masking table.

''dot.f32 instruction has explicit swizzling in operand 1 and operand 2 so masking does not apply to these operands. number of channels is always 3.''

Encoding used in masking table:

Masking table operand 0:

Swizzles (operand 0) dot.f32
Swizzles of operand 0 can not be controled and have predefined combinations described below:

Each channel can be masked with control bits. Masking is described in Swizzle_masking.


 * swz_en, swz_mask1, swz_mask2, swz_mask3

Swizzles (operand 1) dot.f32
Each channel of operand 1 can be precisely controlled with swizzle fields encoded as RSWZ3.


 * op1_swz_c0, op1_swz_c1, op1_swz_c2, op1_swz_c3

Channel 3 can be enabled with bit:


 * c3_en

Swizzles (operand 2) dot.f32
Swizzles of operand 2 can not be precisely controlled and have predefined combinations described below and controlled by swizzle fields:


 * op2_swz, swz_alt_op2

Channel 3 can be enabled with bit:


 * c3_en

Fields (operands) mad.f32

 * swz_alt_op3_2
 * alt_opt0
 * alt_opt1
 * abs_op2
 * op0_strange1
 * op0_strange0
 * swz_mask3
 * swz_mask2
 * swz_mask1
 * swz_en
 * neg_op1
 * abs_op1
 * neg_op3
 * abs_op3
 * swz_alt_op2_2
 * opt0
 * opt1
 * op2i
 * op0
 * swz_alt_op2_x
 * op2_swz
 * swz_alt_op3_x
 * op3_swz
 * op3i
 * swz_alt_op1
 * op1_swz
 * op1

0x20000000 - 0x28000000
Instructions: dot, mov, rsq, rcp, exp, log

Encoding:

Notes:

Having bit 3 in byte 2 set to 0 produces invalid instruction

Fields:

opcode2 (depends on op_sel):

Examples:

0x28000000 - 0x30000000
Instructions: dot, mov, rsq, rcp

Encoding:

Notes:

Having bit 3 in byte 2 set to 0 produces invalid instruction

Fields:

opcode2:

Examples:

0x30000000 - 0x38000000
Instructions: rcp, rsq, log, exp

Encoding:

Notes:

should be omitted if  matches.

Fields:

Examples:

0x38000000 - 0x40000000
Instructions: mov, cmov, cmov8

Encoding:

Notes:

is only applicable to  and   since this is conditional move.

Fields:

Examples:

0x40000000 - 0x48000000
Instructions: pack, (mov)

Encoding:

Notes:

when  matches   it shall be omitted since it has no effect in terms of packing.

furthermore instruction mnemonic shall be replaced to

Fields:

Examples:

0x48000000 - 0x50000000
Instructions: this group only contains illegal instructions

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

0x50000000 - 0x58000000
Instructions: and.u32

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x58000000 - 0x60000000
Instructions: xor.u32

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x60000000 - 0x68000000
Instructions: shl.u32

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x68000000 - 0x70000000
Instructions: shr.u32

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x70000000 - 0x78000000
Instructions: rlp.u32

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x78000000 - 0x80000000
Instructions: this group only contains illegal instructions

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

0x80000000 - 0x88000000
Instructions: add.fx8

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x88000000 - 0x90000000
Instructions: add.fx8, sub.fx8

Encoding:

Notes:

Having bits 2, 3 in byte 2 set to 1 produces invalid instruction

Fields:

Examples:

0x90000000 - 0x98000000
Instructions: add.fx8, sub.fx8, min.fx8, max.fx8

Encoding:

Notes:

Having bit 0 in byte 2 set to 1 produces invalid instruction

Fields:

Examples:

0x98000000 - 0xA0000000
Instructions: mad.u8

Encoding:

Fields:

Examples:

0xA0000000 - 0xA8000000
Instructions: mad

Encoding:

Fields:

Examples:

0xA8000000 - 0xB0000000
Instructions: mad

Encoding:

Fields:

Examples:

0xB0000000 - 0xB8000000
Instructions: this group only contains illegal instructions

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

0xB8000000 - 0xC0000000
Instructions: this group only contains illegal instructions

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

0xC0000000 - 0xC8000000
Instructions: this group only contains illegal instructions

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

0xC8000000 - 0xD0000000
Instructions: mad.u8

Encoding:

Fields:

Examples:

0xD0000000 - 0xD8000000
Instructions: mad

Encoding:

Notes:

Having bit 5 in byte 1 set to 1 produces invalid instruction

Fields:

Examples:

0xD8000000 - 0xE0000000
Instructions: this group only contains illegal instructions

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

0xE0000000 - 0xE8000000
Instructions: tex

Encoding:

Fields:

Examples:

0xE8000000 - 0xF0000000
Instructions: lda32, ldl32, ldt32

Encoding:

Notes:

is only applicable when  modifier is specified

Fields:

Examples:

0xF0000000 - 0xF8000000
Instructions: sta32, stl32, stt32

Encoding:

Notes:

is only applicable when  modifier is specified

Fields:

Examples:

0xF8000000 - 0xFF000000
Notes:

this instruction group is much more complex than others so description is given in form of "glued" truth tables instead of independent truth tables.

predicate 000
Instructions:

Encoding:

Fields:

opcode2:

Examples:

predicate 001
Instructions:

Encoding

Notes:

predicate does not apply to all instructions

Fields

opcode2:

Examples:

predicate 010
Instructions:

Encoding:

Notes:

predicate does not apply to all instructions

Fields

opcode2

Examples:

predicate 011
Instructions:

Encoding

Notes:

predicate does not apply to all instructions

Fields

opcode2

Examples:

predicate 100
Instructions:

Encoding

Notes:

predicate does not apply to all instructions

Fields

opcode2:

Examples:

predicate 101
Instructions:

Encoding

Notes:

predicate does not apply to all instructions

Fields

opcode2:

Examples:

predicate 110
Instructions:

Encoding

Notes:

predicate does not apply to all instructions

Fields

opcode2:

Examples:

predicate 111
Instructions:

Encoding

Notes:

predicate does not apply to all instructions

Fields

opcode2:

Examples: