SceKernelIntrMgr

SceKernelIntrMgr is a kernel module that is primary responsible for setting up external and internal interrupts. Notably, it facilitates communication with the F00D Processor.

Module
This module exists in both non-secure and secure world. The non-secure world SELF can be found in. It also can be found in the Boot Image.

Libraries
This module only exports kernel libraries.

Remove interrupt handler
This function first performs a clear-enable and then removes the current interrupt handler associated with the interrupt.

Clear-enable interrupt
This function writes  to the Interrupt Clear-Enable Registers (offset 0x180 from the Interrupt Distributor registers) at.

Set-enable interrupt
This function writes  to the Interrupt Set-Enable Registers (offset 0x100 from the Interrupt Distributor registers) at.

Set interrupt enabled
Enables or disables an interrupt. If a  is passed to , it acts as Clear-enable interrupt, and if a   is passed, it acts as Set-enable interrupt.

Get interrupt enabled
This function returns whether the interrupt  is enabled or not. If it's enabled, a  will be written to   and a   otherwise. To check the enable status, the function checks the bit number  of the Interrupt Set-Enable register (offset 0x100 from the Interrupt Distributor registers) at.

Get interrupt pending
This function returns whether the interrupt  is pending or not. If it's pending, a  will be returned, and a   will be returned otherwise. To check the pending status, the function checks the bit number  of the Interrupt Set-Pending Registers (offset 0x200 from the Interrupt Distributor registers) at.

Clear interrupt pending
This function writes  to the Interrupt Clear-Pending Registers (offset 0x280 from the Interrupt Distributor registers) at.

Set interrupt priority
This function writes  to the Interrupt Priority Registers (offset 0x400 from the Interrupt Distributor registers) at.

Set processor target
This function writes the bits 0-8 or 16-24 of, depending on whether the mask is in former or the latter bits, to the Interrupt Processor Targets Registers (offset 0x800 from the Interrupt Distributor registers) at

Trigger SGI (Software generated interrupt)
This function triggers a software generated interrupt by writing  to the Software Generated Interrupt Register (offset 0xF00 from the Interrupt Distributor registers). Note:  must be between   and.

Context allowed
If the current "PL1 only Thread ID Register" is  it returns 0, else checks if the current "Multiprocessor Affinity Register" is a target of the interrupt   and returns 1 if it is, and 0 otherwise.

Enable a subinterrupt
It also calls  of the registered   as:.

Calls reg_intr_opt2::fptr2
Calls  of the registered   as:.

Controller
The interrupt controller is defined in the MPCore TRM. The PERIPHBASE address (physical) is 0x1A000000.

Registered Interrupts
As specified in GIC Architecture, interrupt 0-15 are software generated interrupts. There are also no private peripheral interrupts (16-31) implemented. Core Handler indicates which core handles the exception. "All" means it can be handled by any core.