Hardware Timers

The PSVita system embeds 8 Word timers ( to  ) and 6 Longrange timers (  to  ). The timers consist of a counter that gets incremented at a configurable time interval (multiple of a base frequency?), and can generate an interrupt when a certain value is reached.

Most timers are managed by SceSystimer.

Available timers
The  column indicates the physical address at which the interface for a timer is located.

Each timer interface takes 0x1000 bytes.

Misc Reg
Miscellaneous features related to all timers can be accessed from an interface at physical address.

Configuration register
The configuration register is identical for all timers. The period of a Systimer tick is calculated using the following formulas:
 * in seconds (multiply by 10^9 for ns)
 * in Hz (divide by 10^6 for MHz)

is the frequency of the timer's input clock - see below for more information.

Word Timers
Timers with 32-bit counters.

Long Timers
Timers with 64-bit counters.

SceLT5 timer is configured to increment every microsecond (1MHz frequency).

NOTE: On ARMv7 processors that do not support the Large Physical Address Extension, such as the PS Vita's CPU, 64-bit accesses are not guaranteed to be atomic.

This can lead to issues when reading the timer if the low word of a counter is about to overflow.

To ensure the readings from a timer are accurate, use code similar to the following code:

Top Timer
Located at physical address. Called like this because it's the first one in Timer memory region.

The Top timer is a 64-bit timer with the following restrictions:
 * Cannot change the input clock (always SysClock)
 * Doesn't support configuration other than prescale factor
 * All fields other than  and   are RAZ/WI in this timer's configuration register
 * Cannot generate interrupts?