SGX543

General Info
It looks like instructions are 8 bytes long. Roughly speaking - first 4 bytes contain opcode and addressing mode. Second 4 bytes contain operands encoding.

Bit encoding used in this reference:

Predicates
Not sure about predicates yet, but they are used to mask execution of certain instructions.

Notation is the following:

For example:

To reduce amount of examples - they are not listed with predicates.

It is assumed that all predicates are applicable to all instructions in the group unless opposite is indicated.

Operands
Currently - only known form of operands is registers.

Instructions may have up to four operands specified.

In this documentation they will be encoded as:

Registers

 * pa - primary attribute register. 32 bit long.
 * sa - secondary attribute register. 32 bit long.
 * o - output register. 32 bit long.
 * r - temporary register. 32 bit long.
 * i - internal register. 128 bit long.

Register Selector RS2
This encoding uses 2 bits to encode register type.

selector is encoded as:

Note that internal registers are not encoded - they are reserved in Register R6

Register Selector Indexable RSI2
This encoding uses 2 bits to encode register type.

selector is encoded as:

When index mode is used - there has to be another field that encodes index expression with Register Index Offset RIO6

The way that index expression is buit:

Example:

Register R6
This encoding uses 6 bits to encode register index.

register is encoded as:

index is calculated as: value * 2

Register expression is built as:

Example:

Specific type of register can be selected with Register Selector RS2

For destination operand op0 specific type of register can be selected with Register Selector Indexable RSI2

Last 4 values are reserved for internal registers i0, i1, i2, i3

Register Index Offset RIO6
rt is encoded as Register Selector RS2

offset is calculated as: value * 2

offset is encoded as:

Register Swizzle RSWZ2
This encoding uses 2 bits to encode the mask.

selector is encoded as:

swizzle expression is built as:

Example:

Immediate IMM6
Some operands may act as immediate values which are encoded using 6 bits.

Modifier and dest data format
At the moment it is not known which of the data format fields is dest and which is source.

This is the reason why term modifier is mixed with term dest data format.

0x00000000 - 0x08000000
Instructions: mad

Encoding:

Lower 4 bytes

Higher 4 bytes

Notes:

x bits do not affect instruction or operands. might affect something else?

swzy_op0_neg and swz_en can be combined. what does it give?

what if neg_op2 is combined with swzy_op0_neg?

what does {} mean ?

Fields (instruction):

Fields (operands):


 * swzy_op1 - does not have effect on its own. can be used together with swzy_op0_neg to change op1 component to .y . does not have effect with swz_en.

when both swzy_op0_neg and swz_en are enabled - changes second component of op1 to .y


 * alt_opt0 - alter opt0. this bit can be combined with opt0 to produce the following modes for op0:
 * abs_op1 - add abs modifier to op1. example:
 * alt_opt2 - alter opt2. this bit can be combined with opt2 to produce the following modes for op2:
 * alt_opt3 - alter opt3. this bit can be combined with opt3 to produce the following modes for op3:
 * swzy_op3 - does not have effect on its own. can be used together with swzy_op0_neg to change op3 component to .y . does not have effect with swz_en.

when both swzy_op0_neg and swz_en are enabled - changes second component of op3 to .y

or with Register Index Offset RIO6 using index2 mode if specified in alt_opt0. or with Register Index Offset RIO6 using index2 mode if specified in alt_opt2. or IMM6 if specified in alt_opt2. or with Register Index Offset RIO6 using index2 mode if specified in alt_opt3. or IMM6 if specified in alt_opt3.
 * op3_swz - op3 swizzle Register Swizzle RSWZ2. does not have effect on its own. must be used with swz_en or swzy_op0_neg or both.
 * swzy_op2 - does not have effect on its own. can be used together with swzy_op0_neg to change op2 component to .y . does not have effect with swz_en.
 * swzy_op0_neg - changes op0 component to .y . negates each op. enables usage of swizzling mask that is controlled by op1_swz, op2_swz, op3_swz.
 * swz_en - enables usage of swizzling mask that is controlled by op1_swz, op2_swz, op3_swz. swizzle of op0 can not be changed and will allways be .x
 * abs_op2 - add abs modifier to op2. example:
 * neg_op2 - negate op2. example:
 * abs_op3 - add abs modifier to op3. example:
 * neg_op3 - negate op3. example:
 * opt1 - when enabled - selects pa register type. when disabled - selects r register type.
 * opt0 - type of operand op0, encoded with Register Selector Indexable RSI2
 * opt2 - type of operand op2, encoded with Register Selector RS2. or Register Selector Indexable RSI2 if specified in alt_opt2.
 * opt3 - type of operand op3, encoded with Register Selector RS2. or Register Selector Indexable RSI2 if specified in alt_opt3.
 * op0 - op0 encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in opt0.
 * op2_swz - op2 swizzle encoded with Register Swizzle RSWZ2. does not have effect on its own. must be used with swz_en or swzy_op0_neg or both.
 * op1_swz - op1 swizzle encoded with Register Swizzle RSWZ2. does not have effect on its own. must be used with swz_en or swzy_op0_neg or both.
 * op1 - op1 encoded with Register R6
 * op2 - op1 encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in alt_opt2.
 * op3 - op1 encoded with Register R6. or with Register Index Offset RIO6 using index1 mode if specified in alt_opt3.

Examples:

0x08000000 - 0x10000000
Instructions: mul.f32

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x10000000 - 0x18000000
Instructions: mul.f16

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x18000000 - 0x20000000
Instructions: dot.f32, mad.f32

Encoding:

Fields:

Examples:

0x20000000 - 0x28000000
Instructions: dot, mov, rsq, rcp, exp, log

Encoding:

Notes:

Having bit 3 in byte 2 set to 0 produces invalid instruction

Fields:

opcode2 (depends on op_sel):

Examples:

0x28000000 - 0x30000000
Instructions: dot, mov, rsq, rcp

Encoding:

Notes:

Having bit 3 in byte 2 set to 0 produces invalid instruction

Fields:

opcode2:

Examples:

0x30000000 - 0x38000000
Instructions: rcp, rsq, log, exp

Encoding:

Notes:

should be omitted if  matches.

Fields:

Examples:

0x38000000 - 0x40000000
Instructions: mov, cmov, cmov8

Encoding:

Notes:

is only applicable to  and   since this is conditional move.

Fields:

Examples:

0x40000000 - 0x48000000
Instructions: pack, (mov)

Encoding:

Notes:

when  matches   it shall be omitted since it has no effect in terms of packing.

furthermore instruction mnemonic shall be replaced to

Fields:

Examples:

0x48000000 - 0x50000000
Instructions: this group only contains illegal instructions

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

0x50000000 - 0x58000000
Instructions: and.u32

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x58000000 - 0x60000000
Instructions: xor.u32

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x60000000 - 0x68000000
Instructions: shl.u32

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x68000000 - 0x70000000
Instructions: shr.u32

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x70000000 - 0x78000000
Instructions: rlp.u32

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x78000000 - 0x80000000
Instructions: this group only contains illegal instructions

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

0x80000000 - 0x88000000
Instructions: add.fx8

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

Fields:

predicate:

Examples:

0x88000000 - 0x90000000
Instructions: add.fx8, sub.fx8

Encoding:

Notes:

Having bits 2, 3 in byte 2 set to 1 produces invalid instruction

Fields:

Examples:

0x90000000 - 0x98000000
Instructions: add.fx8, sub.fx8, min.fx8, max.fx8

Encoding:

Notes:

Having bit 0 in byte 2 set to 1 produces invalid instruction

Fields:

Examples:

0x98000000 - 0xA0000000
Instructions: mad.u8

Encoding:

Fields:

Examples:

0xA0000000 - 0xA8000000
Instructions: mad

Encoding:

Fields:

Examples:

0xA8000000 - 0xB0000000
Instructions: mad

Encoding:

Fields:

Examples:

0xB0000000 - 0xB8000000
Instructions: this group only contains illegal instructions

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

0xB8000000 - 0xC0000000
Instructions: this group only contains illegal instructions

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

0xC0000000 - 0xC8000000
Instructions: this group only contains illegal instructions

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

0xC8000000 - 0xD0000000
Instructions: mad.u8

Encoding:

Fields:

Examples:

0xD0000000 - 0xD8000000
Instructions: mad

Encoding:

Notes:

Having bit 5 in byte 1 set to 1 produces invalid instruction

Fields:

Examples:

0xD8000000 - 0xE0000000
Instructions: this group only contains illegal instructions

Encoding:

{|
 * - style="vertical-align:top;"


 * }
 * }

0xE0000000 - 0xE8000000
Instructions: tex

Encoding:

Fields:

Examples:

0xE8000000 - 0xF0000000
Instructions: lda32, ldl32, ldt32

Encoding:

Notes:

is only applicable when  modifier is specified

Fields:

Examples:

0xF0000000 - 0xF8000000
Instructions: sta32, stl32, stt32

Encoding:

Notes:

is only applicable when  modifier is specified

Fields:

Examples:

0xF8000000 - 0xFF000000
Notes:

this instruction group is much more complex than others so description is given in form of "glued" truth tables instead of independent truth tables.

predicate 000
Instructions:

Encoding:

Fields:

opcode2:

Examples:

predicate 001
Instructions:

Encoding

Notes:

predicate does not apply to all instructions

Fields

opcode2:

Examples:

predicate 010
Instructions:

Encoding:

Notes:

predicate does not apply to all instructions

Fields

opcode2

Examples:

predicate 011
Instructions:

Encoding

Notes:

predicate does not apply to all instructions

Fields

opcode2

Examples:

predicate 100
Instructions:

Encoding

Notes:

predicate does not apply to all instructions

Fields

opcode2:

Examples:

predicate 101
Instructions:

Encoding

Notes:

predicate does not apply to all instructions

Fields

opcode2:

Examples:

predicate 110
Instructions:

Encoding

Notes:

predicate does not apply to all instructions

Fields

opcode2:

Examples:

predicate 111
Instructions:

Encoding

Notes:

predicate does not apply to all instructions

Fields

opcode2:

Examples: