SceKernelIntrMgr

SceKernelIntrMgr is a kernel module that is primary responsible for setting up external and internal interrupts. Notably, it facilitates communication with the F00D Processor.

Module
This module exists in both non-secure and secure world. The non-secure world SELF can be found in. It also can be found in the Boot Image.

Libraries
This module only exports kernel libraries.

sceKernelReleaseIntrHandlerForDriver
This function first performs a disable and then removes the current interrupt handler associated with the interrupt.

sceKernelDisableIntrForDriver
This function writes  to the Interrupt Disable Registers (offset 0x180 from the Interrupt Distributor registers) at.

sceKernelEnableIntrForDriver
This function writes  to the Interrupt Enable Registers (offset 0x100 from the Interrupt Distributor registers) at.

sceKernelResumeIntrForDriver
Enables or disables an interrupt. If a  is passed to , it acts as sceKernelDisableIntrForDriver, and if a   is passed, it acts as sceKernelEnableIntrForDriver.

sceKernelSuspendIntrForDriver
This function returns whether the interrupt  is enabled or not. If it's enabled, a  will be written to   and a   otherwise. To check the enable status, the function checks the bit number  of the Interrupt Enable register (offset 0x100 from the Interrupt Distributor registers) at.

sceKernelGetIntrPendingStatusForDebuggerForDriver
This function returns whether the interrupt  is pending or not. If it's pending, a  will be returned, and a   will be returned otherwise. To check the pending status, the function checks the bit number  of the Interrupt Set-Pending Registers (offset 0x200 from the Interrupt Distributor registers) at.

sceKernelClearIntrPendingStatusForDebuggerForDriver
This function writes  to the Interrupt Clear-Pending Registers (offset 0x280 from the Interrupt Distributor registers) at.

sceKernelSetIntrPriorityForDriver
This function writes  to the Interrupt Priority Registers (offset 0x400 from the Interrupt Distributor registers) at.

sceKernelSetIntrTargetCpuForDriver
This function writes the bits 0-8 or 16-24 of, depending on whether the mask is in former or the latter bits, to the Interrupt Processor Targets Registers (offset 0x800 from the Interrupt Distributor registers) at

sceKernelGenerateSoftIntrForDriver
This function triggers a SGI (software generated interrupt) by writing  to the Software Generated Interrupt Register (offset 0xF00 from the Interrupt Distributor registers, physical address 0x1A001F00). Note:  must be between   and.

sceKernelIsIntrContextForDriver
If the current "PL1 only Thread ID Register" is  it returns 0, else checks if the current "Multiprocessor Affinity Register" is a target of the interrupt   and returns 1 if it is, and 0 otherwise.

sceKernelCallSubIntrHandlerForDriver
Triggers a subinterrupt by directly calling it.

sceKernelEnableSubIntrForDriver
It also calls  of the registered   as:.

sceKernelDisableSubIntrForDriver
Calls  of the registered   as:.

sceKernelSuspendSubIntrForDriver
Calls  of the registered   as:.

allocate_syscall_table
Calls sceKernelAllocPartitionMemBlockForKernel(0x10009, "SceSyscallTable", 0x1020D006, 4 * a1, unk);.

get_intr_logs
Read Physical_Memory and writes logs to str_buf.

SceIntrmgrForTZS
sceKernelRegisterIntrHandler: found sceKernelReleaseIntrHandler: found sceKernelEnableIntr: found sceKernelDisableIntr: found sceKernelIsIntrContext: found sceKernelRegisterMonitorCallHandler: found sceKernelGenerateSoftIntr: found sceKernelUsleep: found

NID 0: 0x28BBA975: sceKernelGenerateSoftIntr NID 1: 0x4F39B381: sceKernelDisableIntr NID 2: 0x636F4549: sceKernelIsIntrContext NID 3: 0x6B84DA8F: sceKernelRegisterIntrHandler NID 4: 0x75A0F189: sceKernelReleaseIntrHandler NID 5: 0x9168E78E NID 6: 0x92DE2E92 NID 7: 0x98E38390: sceKernelEnableIntr NID 8: 0xAA3C4787 NID 9: 0xBFBEAB5C NID 10: 0xC0908EA9: sceKernelUsleep NID 11: 0xC188114F: sceKernelRegisterMonitorCallHandler NID 12: 0xF3B92D98 NID 13: 0xFEAC9841

sceKernelRegisterMonitorCallHandlerForTZS
Register SMC call (secure only).

Controller
The interrupt controller is defined in the MPCore TRM. The PERIPHBASE address (physical) is 0x1A000000.

Registered Interrupts
As specified in GIC Architecture, interrupt 0-15 are software generated interrupts. There are also no private peripheral interrupts (16-31) implemented. Core Handler indicates which core handles the exception. "All" means it can be handled by any core.