DMAC

Direct Memory Access Controller

The DMA controllers can be used to perform memory copy operations in the background without CPU overhead. Some DMACs can also be used to perform hardware-accelerated cryptography / hashing / RNG. On ARM, the SceKernelDmacMgr module is responsible for commanding the DMACs.

MMIO Interface
The DMACs interfaces are mapped at the following locations:

Standard DMACs
DMAC0, DMAC1, DMAC2, DMAC3 and DMAC6 fall under this category.

These DMACs have two channels and can only be used for  and   operations - all other commands do not operate properly.

Each channel delivers interrupts with its own ID: for example, DMAC0 Channel 0 delivers interrupts via ID 0x70 and Channel 1 via ID 0x71.

DMAC4
Mostly identical to standard DMACs except it has 16 channels; for this reason, the MMIO interface is different.

Interrupts are also grouped by groups of 4 channels e.g. ID 0x78 corresponds to channels 0~3, 0x79 corresponds to channels 4~7, etc.

DMAC5
DMAC5 can perform all cryptographic, hashing and RNG operations in addition to the ones provided by other DMACs.

DMAC5 Key Ring
A keyring is located on the same bus as DMAC5 and can be used for some operations. This device is located at physical address.

The DMAC5 key ring holds 32 keys of 256 bits each and can be accessed by ARM and CMeP. Configuration registers control which slots can be read by ARM in Non-Secure state ?and which slots can be used by DMAC5 for operations?.

The key ring configuration is set during secure bootSKBL?. On bootcoldboot? reset?,  defaults to   which indicates slots  and   are accessible by the Non-Secure kernel; the   register is set to.

Bigmac
Bigmac is only accessible by CMeP (?)

Bigmac doesn't have doesn't support DES.

Bigmac Key Ring
See Cmep Key Ring Base.

Usage
DMA controllers can be programmed via the MMIO interface for a one-shot operation, or controlled by so-called DMA tag lists for more complex operations.

While DMACs can ensure coherency at L2 cache level, they are not MMU-aware - all addresses provided to the DMACs must be physical addresses.

One-shot operation
Simple DMA transfers can be performed using only the DMACs' MMIO interface.


 * 1) Ensure the DMA channel is inactive
 * 2) * Read the  register and check bit 0
 * 3) * You can cancel the current DMA transfer by writing 0 to the  register
 * 4) Prepare the new transfer by writing to the configuration registers
 * 5) * For example, to perform a SET command, fill the,  ,   and   registers appropriately
 * 6) Start the transfer
 * 7) * Write 1 to the  register
 * 8) Wait for the transfer to complete
 * 9) * If using interrupts read and write back the value of the interrupt status register
 * 10) * Unrelated work may be carried out in parallel with the DMA transfer

Example code in C:

Chained operation
Complex DMA transfers can be performed using DMA tag lists instead of the MMIO interface.

As an example, the  routine performs a copy from one virtually contiguous buffer to another. However, the buffers may be physically fragmented and DMACs are not MMU-aware; thus the copy may have to be performed in multiple rounds.

To this end, a DMA tag list may be written to memory first then sent to the DMAC which will execute all the tags in the list one after another. The DMA tag structure contains all the data required for an operation along with a link to another tag to allow chaining.

To start a chained transfer, write the physical address of the first DMA tag in a chain to the  register.

Interrupts
An interrupt is delivered when a command with bit 0x1000 set completes or when an error occurs.

Error handling
When a DMAC error occurs, ?an interrupt is triggered? and bit  is set in the   register, and further information about the error can be found in this same register. If a chained operation was ongoing, the  register will contain the physical address of the DMA tag that was being executed.

Supported commands
N.B. This is the list of all existing commands. See the description of each DMAC to know which commands it supports.

Also see here.