Pervasive

Pervasive is a device that controls the clocks of most of the devices of the system.

ScePervasiveMisc (0xE3100000)
Devices can be fully disabled? by writing a 1 to the corresponding bit of the ScePervasiveMisc (PA ) register. To disable the device, do.

revision0
Returned by SceLowio, read by SKBL/NSKBL/...

Contains the Kermit revision (see sceKernelSysrootGetKermitRevisionForKernel) and other information.

ScePervasiveReset (0xE3101000)
Devices must be put out of reset (device reset disabled) before they are first used.

To enable reset of a device (put a device in reset), do.

To disable reset of a device (put a device out of reset), do.

ScePervasiveGate (0xE3102000)
Devices can be clock gated to preserve battery.

To enable clock gate (request the clock of a device to be enabled), do.

To disable clock gate (request the clock of a device to be disabled), do.

ScePervasiveVid (0xE3104000)
Voltage integer data

Base Clock
Registers at physical address  (ScePervasiveBaseClk).

ARM Clocks
The ARM core clock and L2 cache clock consist of two registers 0xE2103000 and 0xE2103004.

Register 0xE2103000 selects the base clock frequency.

It seems that 42-freq is selected internally when Undefined index is selected

Register 0xE2103004 adjusts the selected base clock frequency.

0xE2103004 sets the index that adjusts the base clock frequency.

It seems that the adjustment can be expressed by the following formula.

adjust_index ranges from 0 to 8. Selecting 9 or higher selects 0 internally.

Also a joke-like approximation :.

However, not sure if this formula is completely correct, but It can see that it is very close to the value of yifan's clock analyzer.

ARM Clocks (by yifan's clock analyzer)
The ARM CPU clocks are controlled by two registers at physical address  (ScePervasiveBaseClk). Currently, it is unknown how the values are interpreted. However,  (one word) takes values 0 to 16, and increases clock speed while   (single byte) takes values 0 to 8 and decreases clock speed. It is likely related to a PLL multiply and divide function. The input clock signal comes from a P1P40167 clock synthesizer (found on the bottom of the board under the main SoC). It takes a 27MHz crystal and generates a 37MHz clock which feeds directly into the SoC's internal PLL.

The following are tests run to determine what the values of each register corresponds to. It appears that the maximum clock speed is 499MHz and the minimum clock speed is 16MHz.

'''These clocks may be wrong. "Kernel Clock Speed" is "Clock Speed + 5". However, there is an error of ± 5 to 6 in "Clock Speed".'''

VENEZIA Clock
The register at physical address  seems to control the clock frequency of VENEZIA.

CMeP Clock
The low 8 bits of the register at physical address  control CMeP clock speed, and Main Xbar, I/O Bus speed too. This was guessed because it is used in a -like function to calculate the input for a   function.

Testing was performed using SceLT5 as a time reference (µs-accurate), and compared against the hardcoded table in.

sets the register to 0x10005, meaning CMeP usually runs at 83MHz.