Pervasive

Pervasive is a device that controls the clocks of most of the devices of the system.

ScePervasiveMisc (0xE3100000)
Devices can be fully disabled? by writing a 1 to the corresponding bit of the ScePervasiveMisc (PA ) register. To disable the device, do.

"SoC revision"
Returned by SceLowio, read by SKBL/NSKBL/...

Contains the Kermit revision (see sceKernelSysrootGetKermitRevisionForKernel) and other information.

ScePervasiveReset (0xE3101000)
Devices must be put out of reset (device reset disabled) before they are first used.

To enable reset of a device (put a device in reset), do.

To disable reset of a device (put a device out of reset), do.

ScePervasiveGate (0xE3102000)
Devices can be clock gated to preserve battery.

To enable clock gate (request the clock of a device to be enabled), do.

To disable clock gate (request the clock of a device to be disabled), do.

Devices
The offsets and masks of Pervasive devices are documented below. Some devices appear to only be accessible in secure world.

Base Clock
Registers at physical address  (ScePervasiveBaseClk).

ARM Clocks
The ARM CPU clocks are controlled by two registers at physical address  (ScePervasiveBaseClk). Currently, it is unknown how the values are interpreted. However,  (one word) takes values 0 to 16, and increases clock speed while   (single byte) takes values 0 to 8 and decreases clock speed. It is likely related to a PLL multiply and divide function. The input clock signal comes from a P1P40167 clock synthesizer (found on the bottom of the board under the main SoC). It takes a 27MHz crystal and generates a 37MHz clock which feeds directly into the SoC's internal PLL.

The following are tests run to determine what the values of each register corresponds to. It appears that the maximum clock speed is 499MHz and the minimum clock speed is 16MHz.

'''These clocks may be wrong. "Kernel Clock Speed" is "Clock Speed + 5". However, there is an error of ± 5 to 6 in "Clock Speed".'''

CMeP Clock
The low 8 bits of the register at physical address  seem to control CMeP clock speed. This was guessed because it is used in a -like function to calculate the input for a   function.

The following data comes from a hardcoded table:

sets the register to 5, meaning CMeP should run at 83MHz.

VENEZIA Clock
The register at physical address  seems to control the clock frequency of VENEZIA.