Memory System

Kermit memory system internals

This is all based on assumptions and may be completely wrong.

Terminology
A device connected to the memory system. An interface between an Agent and the memory Short for Target Access? Short for Initiator Access? A data exchange performed via the memory bus system. Transactions transfer data between an IA and a TA. A transaction from X (an IA) to Y (a TA) is initiated by X and targets Y. Short for time-shared bus. A link between agents on which a single transaction may be in progress at a time. Short for Crossbar. A link between agents on which multiple transactions may be in progress at a time (as long as they do not target the same TA). This could be a single physical device of the memory system that allocates access to the bus/XBar to IAs (most plausible hypothesis). However, the PS Vita may instead be using a decentralized bus arbitration system in which there is no single arbiter. When a transaction is occurring on a bus, the agent that started the transaction is referred to as the Bus Master.
 * Agent
 * Access
 * TA
 * IA
 * Transaction
 * Bus
 * XBar
 * Arbiter
 * Bus Master

There are three revisions of the memory system layout: One for Kermit1.0 ES1, one for Kermit1.0 ES2 (not documented but close to ES3) and one for Kermit1.0 ES3, ES4, and Kermit1.5 ES1.

In the following sections, you may see register names such as  and   mentioned. Unless otherwise specified, a register prefixed with  is merely the ARM Secure variant of the register (e.g.   is   for ARM Secure). Everything that applies to a register should apply to its Secure variant, except that the register is updated by Secure bus transactions, instead of Non-Secure bus transactions.

Control registers
There are several MMIO registers available to alter the behavior of the memory system, or query information about the memory system's state.

IA/TA registers
A common register group associated to every IA or TA of the memory system. The register group is 0x1000 bytes sized (but maybe not all room is used).

(List of physical address for all these interfaces can be found on Physical Memory page - names start with  - will be migrated here at some point)

Bus Errors
When a bus error occurs, an interrupt is delivered to ARM Secure (Interrupt ID 0x21=33) or Non-Secure (Interrupt ID 0x20=32). The OS considers all bus errors to be fatal. The interrupt handlers installed for these IDs perform a register dump then stop the system.

It appears that device-initiated bus errors (e.g. DMAC) are always routed to Non-Secure interrupt. There may be other rules to consider (e.g. some register to set whether a device is Secure/Non-Secure).

It is unknown whether or not CMeP can receive bus error interrupts or how CMeP fits in the memory system.

Bus Error Attribute
The bus error attribute is a 32-bit value that can be recovered in a per-device MMIO register (along with the bus error address).

The attribute holds multiple informations: who was the bus master when the error occurred, what bus command was ongoing, and (sometimes) the reason of the bus error.

Note that for some devices (Spad32K, Spad128K, Compati SRAM), the only valid attribute is, indicating an invalid address.

To decode the meaning of  and , shift them by 16 and 8 respectively to obtain a value between 0-63/0-7 and use the following tables:

Clear TA error
In old firmwares (e.g. 0.920 - pre-ES3, so this may no longer be valid), there exists inside the bus error module a function named  which works the following way.

First, choose a bus/XBar that will serve as start point (MainXBar for ES2). Second, recursively build a list of all TAs connected to this start point. Repeat the process for all TAs that are busses or XBars. Third, walk the obtained tree. Check the  of all TAs. If an error is present, repeat the procedure recursively (if bus/XBar) then clear the error.

To detect an error, check if bit  is present in  To clear the error, simply write   to.

NOTE: old firmwares do not have informations about IAs, only TAs. This could explain the routine's name, but also means this procedure may also work/be needed on IA side.

Misc
The memory system is able to distinguish if a transaction is originating from ARM Secure state or Non-Secure state because ARM Cortex-A9 processors with Security Extensions have an additional bit indicating whether the access is Secure or Non-Secure added to all memory system transactions.

?All devices on the Kermit bus diagram that have an IA are treated as ARM NS.? (attempting to perform a DMAC memcpy from Secure to Non-Secure LPDDR0 region results in a NS bus error)

On ES1 hardware, the bus registers are prefixed with  instead of. The meaning of both these acronyms is unknown.