IFTU Registers: Difference between revisions
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| 0x180 | | 0x180 | ||
| 4 | | 4 | ||
| Some flags | | Some flags (bilinear filter) | ||
|- | |- | ||
| 0x200 + n * 0x100 + 0x00 | | 0x200 + n * 0x100 + 0x00 |
Revision as of 07:49, 25 June 2020
MMIO Interfaces
Name | Physical address |
---|---|
SceIftu0RegA (OLED FB) | 0xE5020000 |
SceIftu0RegB | 0xE5021000 |
SceIftuc0Reg | 0xE5022000 |
SceIftu1RegA (HDMI FB) | 0xE5030000 |
SceIftu1RegB | 0xE5031000 |
SceIftuc1Reg | 0xE5032000 |
SceIftu2Reg | 0xE5040000 |
Registers
SceIftu0RegA, SceIftu0RegB, SceIftu1RegA, SceIftu0RegB (plane registers)
Offset | Size | Description |
---|---|---|
0x000 | 4 | Control register: bit 0 = enable?, bit 2 = ??, bit 3 = ?? |
0x004 | 4 | CRTC mask: bit 0 = enable scanout to engine/CRTC of OLED/LCD, bit 1 = enable scanout to engine/CRTC of HDMI |
0x040 | 4 | Interrupts (read = triggered interrupts, write = clear interrupt) |
0x050 | 4 | Interrupt enable. bit 0 = first plane, bit 1 = second plane |
0x054 | 4 | ?? |
0x058 | 4 | ?? |
0x08C | 4 | Alpha value (transparency) from 0x00 to 0xFF |
0x0A0 | 4 | Alpha control: (bit 0 = disable alpha blending) |
0x100 | 4 | CSC Control. bit 0 = enable CSC |
0x104 | 4 | CSC unknown |
0x108 | 4 | CSC unknown |
0x10C | 4 | CSC rr, S3.9 fixed point format |
0x110 | 4 | CSC rg, S3.9 fixed point format |
0x114 | 4 | CSC rb, S3.9 fixed point format |
0x118 | 4 | CSC gr, S3.9 fixed point format |
0x11C | 4 | CSC gg, S3.9 fixed point format |
0x120 | 4 | CSC gb, S3.9 fixed point format |
0x124 | 4 | CSC br, S3.9 fixed point format |
0x128 | 4 | CSC bg, S3.9 fixed point format |
0x12C | 4 | CSC bb, S3.9 fixed point format |
0x130 | 4 | CSC post-multiplication add (fb plane 0), 10-bit int |
0x134 | 4 | CSC post-multiplication add (fb planes 1 and 2), 10-bit int |
0x138 | 4 | CSC rr, S3.9 fixed point format |
0x13C | 4 | CSC rg, S3.9 fixed point format |
0x140 | 4 | CSC rb, S3.9 fixed point format |
0x144 | 4 | CSC gr, S3.9 fixed point format |
0x148 | 4 | CSC gg, S3.9 fixed point format |
0x14C | 4 | CSC gb, S3.9 fixed point format |
0x150 | 4 | CSC br, S3.9 fixed point format |
0x154 | 4 | CSC bg, S3.9 fixed point format |
0x158 | 4 | CSC bb, S3.9 fixed point format |
0x15C | 4 | CSC post-multiplication clamp range max (fb plane 0), 10-bit int |
0x160 | 4 | CSC post-multiplication clamp range min (fb plane 0), 10-bit int |
0x164 | 4 | CSC post-multiplication clamp range max (fb planes 1 and 2), 10-bit int |
0x168 | 4 | CSC post-multiplication clamp range min (fb planes 1 and 2), 10-bit int |
0x180 | 4 | Some flags (bilinear filter) |
0x200 + n * 0x100 + 0x00 | 4 | Source plane 0 physical address |
0x200 + n * 0x100 + 0x04 | 4 | Source plane 1 physical address |
0x200 + n * 0x100 + 0x08 | 4 | Source plane 2 physical address |
0x200 + n * 0x100 + 0x40 | 4 | Source pixelformat (0x10 = A8B8G8R8) |
0x200 + n * 0x100 + 0x44 | 4 | Source width (aligned to 16) |
0x200 + n * 0x100 + 0x48 | 4 | Source height (aligned to 8) |
0x200 + n * 0x100 + 0x4C | 4 | Control register. bit 0 = disable plane |
0x200 + n * 0x100 + 0x54 | 4 | Source leftover stride, ((pitch - aligned_width) * bpp)
|
0x200 + n * 0x100 + 0x58 | 4 | Source leftover align, if YCbCr: (width >> 1) & 0xF (Chroma align?)
|
0x200 + n * 0x100 + 0x60 | 4 | Framebuffer vertical top padding |
0x200 + n * 0x100 + 0x64 | 4 | Framebuffer vertical bottom padding |
0x200 + n * 0x100 + 0x68 | 4 | Framebuffer horizontal left padding |
0x200 + n * 0x100 + 0x6C | 4 | Framebuffer horizontal right padding |
0x200 + n * 0x100 + 0x80 | 4 | Destination plane 0 physical address |
0x200 + n * 0x100 + 0x84 | 4 | Destination plane 1 physical address |
0x200 + n * 0x100 + 0x88 | 4 | Destination plane 2 physical address |
0x200 + n * 0x100 + 0xA0 | 4 | Destination pixelformat |
0x200 + n * 0x100 + 0xA4 | 4 | Destination width |
0x200 + n * 0x100 + 0xA8 | 4 | Destination height |
0x200 + n * 0x100 + 0xB4 | 4 | Destination leftover stride, ((pitch - aligned_width) * bpp)
|
0x200 + n * 0x100 + 0xB8 | 4 | Destination leftover align, if YCbCr: (width >> 1) & 0xF (Chroma align?)
|
0x200 + n * 0x100 + 0xC0 | 4 | Scanout source width in 16.16 fixed point ratio of the destination width |
0x200 + n * 0x100 + 0xC4 | 4 | Scanout source height in 16.16 fixed point ratio of the destination width |
0x200 + n * 0x100 + 0xC8 | 4 | Scanout destination X |
0x200 + n * 0x100 + 0xCC | 4 | Scanout destination Y |
0x200 + n * 0x100 + 0xD0 | 4 | Scanout source X in 4.4 fixed point |
0x200 + n * 0x100 + 0xD4 | 4 | Scanout source Y in 4.4 fixed point |
SceIftuc0Reg, SceIftuc1Reg (control registers)
Offset | Size | Description |
---|---|---|
0x00 | 4 | Control register. bit 0 = enable engine. |
0x04 | 4 | Plane control register. bit 0 = enable alpha blending, bit 2 = enable first plane, bit 4 = enable second plane. |
0x10 | 4 | RegA configuration selector: bit 0 = Use the first (offset 0x2XX) or second (offset 0x3XX) configuration |
0x14 | 4 | RegA unk |
0x18 | 4 | RegB configuration selector: bit 0 = Use the first (offset 0x2XX) or second (offset 0x3XX) configuration |
0x1C | 4 | RegB unk |
0x20 | 4 | Blending control register. bit 1 = additive blending. bit 0 = subtractive blending. |
Pixelformats
Format | Value |
---|---|
BGR565 | 0x01 |
RGB565 | 0x02 |
BGRA5551 | 0x04 |
RGBA5551 | 0x08 |
BGRX8888 | 0x10 |
RGBX8888 | 0x20 |
BGRA1010102 | 0x40 |
RGBA1010102 | 0x80 |
BGRP | 0x100 |
RGBX8888_MULT | 0x1000 |
BGRX8888_MULT | 0x2000 |
RGBA1010102_MULT | 0x4000 |
RGBA1010102_MULT | 0x8000 |
NV12 | 0x10000 |
YCBCR420 | 0x20000 |
YCBCR422 | 0x200000 |