Difference between revisions of "Caches"
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(→Configured values: Add RAM Latency values) |
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| Line 32: | Line 32: | ||
| 0x60090001 | | 0x60090001 | ||
| Auxiliary Control Register | | Auxiliary Control Register | ||
| + | |- | ||
| + | | 0x108 | ||
| + | | 0x00000000 | ||
| + | | Tag RAM Latency Control Register | ||
| + | |- | ||
| + | | 0x10C | ||
| + | | 0x00000131 | ||
| + | | Data RAM Latency Control Register | ||
|} | |} | ||
[[Category:MMIO]] | [[Category:MMIO]] | ||
Revision as of 04:13, 13 January 2024
PL310 L2 Cache
The Vita uses the PL310 r3p1-50rel0 L2 cache (Cache ID Register = 0x410000C7) is is mapped to 0x1A002000.
RO Registers values
| Offset | Value | Name |
|---|---|---|
| 0x000 | 0x410000C7 | Cache ID Register |
| 0x004 | 0x1E440440 | Cache Type Register |
Configured values
| Offset | Value | Name |
|---|---|---|
| 0x100 | 0x00000001 | Control Register |
| 0x104 | 0x60090001 | Auxiliary Control Register |
| 0x108 | 0x00000000 | Tag RAM Latency Control Register |
| 0x10C | 0x00000131 | Data RAM Latency Control Register |