Difference between revisions of "Caches"
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(Created page with "= PL310 L2 Cache = The Vita uses the [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246f/index.html PL310 r3p1-50rel0] L2 cache (Cache ID Register = 0x410000...") |
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Line 16: | Line 16: | ||
| 0x1E440440 | | 0x1E440440 | ||
| Cache Type Register | | Cache Type Register | ||
+ | |} | ||
+ | |||
+ | == Configured values == | ||
+ | {| class='wikitable' | ||
+ | |- | ||
+ | ! Offset | ||
+ | ! Value | ||
+ | ! Name | ||
+ | |- | ||
+ | | 0x100 | ||
+ | | 0x00000001 | ||
+ | | Control Register | ||
+ | |- | ||
+ | | 0x104 | ||
+ | | 0x60090001 | ||
+ | | Auxiliary Control Register | ||
|} | |} |
Revision as of 22:29, 13 July 2017
PL310 L2 Cache
The Vita uses the PL310 r3p1-50rel0 L2 cache (Cache ID Register = 0x410000C7) is is mapped to 0x1A002000
.
RO Registers values
Offset | Value | Name |
---|---|---|
0x000 | 0x410000C7 | Cache ID Register |
0x004 | 0x1E440440 | Cache Type Register |
Configured values
Offset | Value | Name |
---|---|---|
0x100 | 0x00000001 | Control Register |
0x104 | 0x60090001 | Auxiliary Control Register |