Difference between revisions of "DSI Registers"
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| (One intermediate revision by the same user not shown) | |||
| Line 19: | Line 19: | ||
! Description | ! Description | ||
|- | |- | ||
| − | | | + | | 0x00C |
| 4 | | 4 | ||
| Clock related | | Clock related | ||
|- | |- | ||
| − | | | + | | 0x014 |
| 4 | | 4 | ||
| Interrupts (read = triggered interrupts, write = clear interrupt) | | Interrupts (read = triggered interrupts, write = clear interrupt) | ||
| + | |- | ||
| + | | 0x030 | ||
| + | | 4 | ||
| + | | bits[31:16] = Vertical Back Porch | ||
| + | |- | ||
| + | | 0x500 | ||
| + | | 4 | ||
| + | | Command FIFO. | ||
|} | |} | ||
Revision as of 18:18, 18 July 2017
MMIO Interfaces
| Name | Physical address |
|---|---|
| SceDsi0Reg | 0xE5050000 |
| SceDsi1Reg | 0xE5060000 |
Registers
| Offset | Size | Description |
|---|---|---|
| 0x00C | 4 | Clock related |
| 0x014 | 4 | Interrupts (read = triggered interrupts, write = clear interrupt) |
| 0x030 | 4 | bits[31:16] = Vertical Back Porch |
| 0x500 | 4 | Command FIFO. |