Difference between revisions of "GPIO Registers"
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| Line 22: | Line 22: | ||
| 4 | | 4 | ||
| Port mode (1 bit each port) | | Port mode (1 bit each port) | ||
| + | |- | ||
| + | | 0x04 | ||
| + | | 4 | ||
| + | | ?? (1 bit each port) | ||
|- | |- | ||
| 0x08 | | 0x08 | ||
| Line 38: | Line 42: | ||
| 4 | | 4 | ||
| Interrupt mode (2 bits) for interrupts 16-31 | | Interrupt mode (2 bits) for interrupts 16-31 | ||
| + | |- | ||
| + | | 0x34 | ||
| + | | 4 | ||
| + | | ?? (1 bit each port) | ||
|} | |} | ||
Revision as of 23:54, 13 February 2017
MMIO Interfaces
| Name | Physical address |
|---|---|
| SceGpio0Reg | 0xE20A0000 |
| SceGpio1Reg | 0xE0100000 |
Registers
| Offset | Size | Description |
|---|---|---|
| 0x00 | 4 | Port mode (1 bit each port) |
| 0x04 | 4 | ?? (1 bit each port) |
| 0x08 | 4 | Port set (1 bit each port) |
| 0x0C | 4 | Port clear (1 bit each port) |
| 0x14 | 4 | Interrupt mode (2 bits) for interrupts 0-15 |
| 0x18 | 4 | Interrupt mode (2 bits) for interrupts 16-31 |
| 0x34 | 4 | ?? (1 bit each port) |