IFTU Registers

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MMIO Interfaces

Name Physical address
SceIftu0RegA (OLED FB) 0xE5020000
SceIftu0RegB 0xE5021000
SceIftuc0Reg 0xE5022000
SceIftu1RegA (HDMI FB) 0xE5030000
SceIftu1RegB 0xE5031000
SceIftuc1Reg 0xE5032000
SceIftu2Reg 0xE5040000

It looks like the display controller has 4 overlay planes (Iftu0RegA, Iftu0RegB, Iftu1RegA, Iftu0RegB) and 1 cursor plane (Iftu2Reg)?

Registers

IftuRegs

Offset Size Description
0x000 4 Control register: bit 0 = enable?, bit 2 = ??, bit 3 = ??
0x004 4 CRTC mask: bit 0 = enable scanout to engine/CRTC of OLED/LCD, bit 1 = enable scanout to engine/CRTC of HDMI
0x040 4 Interrupts (read = triggered interrupts, write = clear interrupt)
0x050 4 Interrupt enable. bit 0 = first plane, bit 1 = second plane
0x08C 4 Alpha value (transparency) from 0x00 to 0xFF
0x0A0 4 Alpha control: (bit 0 = disable alpha blending)
0x180 4 Some flags
0x200 + n * 0x100 + 0x00 4 Physical address
0x200 + n * 0x100 + 0x04 4 Unknown
0x200 + n * 0x100 + 0x24 4 Scanout source X (in (0x100000 / 960) multiples)
0x200 + n * 0x100 + 0x28 4 Scanout source Y (in (0x100000 / 544) multiples)
0x200 + n * 0x100 + 0x40 4 Pixelformat (0x10 = A8B8G8R8)
0x200 + n * 0x100 + 0x44 4 Buffer width (aligned to 16)
0x200 + n * 0x100 + 0x48 4 Buffer height (aligned to 8)
0x200 + n * 0x100 + 0x4C 4 Control register. bit 0 = disable plane?
0x200 + n * 0x100 + 0x54 4 Leftover stride
0x200 + n * 0x100 + 0x58 4 ??
0x200 + n * 0x100 + 0x60 4 Vertical front porch
0x200 + n * 0x100 + 0x64 4 Vertical back porch
0x200 + n * 0x100 + 0x68 4 Horizontal front porch
0x200 + n * 0x100 + 0x6C 4 Horizontal back porch
0x200 + n * 0x100 + 0x24 4 Scanout source width (in (0x100000 / 960) multiples)
0x200 + n * 0x100 + 0xC4 4 Scanout source height (in (0x100000 / 544) multiples)
0x200 + n * 0x100 + 0xC8 4 Scanout destination X
0x200 + n * 0x100 + 0xCC 4 Scanout destination Y
0x200 + n * 0x100 + 0xD0 4 Scanout destination width
0x200 + n * 0x100 + 0xD0 4 Scanout destination height

Where n can be 0 and 1. n = 0 configures the CRTC 0 (OLED/LCD) scanout, n = 1 configures the CRTC 1 (HDMI) scanout?

IftucRegs (control registers?)

Offset Size Description
0x00 4 Control register. bit 0 = enable engine.
0x04 4 Plane control register. bit 0 = enable alpha blending, bit 2 = enable first plane, bit 4 = enable second plane.
0x10 + i * 0x8 + 0x00 4 bit 0 = Enable Engine 0 (OLED/LCD) or Engine 1 (HDMI) ?
0x10 + i * 0x8 + 0x04 4 ??
0x20 4 Alpha control register. bit 2 = enable alpha blending.

Where i can be 0 or 1 for RegA or RegB.