Difference between revisions of "IFTU Registers"
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| Line 37: | Line 37: | ||
| 0x004 | | 0x004 | ||
| 4 | | 4 | ||
| − | | bit 1 = | + | | bit 1 = engine/CRTC to attach to (0 = OLED/LCD, 1 = HDMI) |
|- | |- | ||
| 0x090 | | 0x090 | ||
Revision as of 11:07, 17 July 2017
MMIO Interfaces
| Name | Physical address |
|---|---|
| SceIftu0RegA (OLED FB) | 0xE5020000 |
| SceIftu0RegB | 0xE5021000 |
| SceIftuc0Reg | 0xE5022000 |
| SceIftu1RegA (HDMI FB) | 0xE5030000 |
| SceIftu1RegB | 0xE5031000 |
| SceIftuc1Reg | 0xE5032000 |
| SceIftu2Reg | 0xE5040000 |
Registers
IftuRegs
| Offset | Size | Description |
|---|---|---|
| 0x004 | 4 | bit 1 = engine/CRTC to attach to (0 = OLED/LCD, 1 = HDMI) |
| 0x090 | 4 | Brightness value (or alpha?) |
| 0x0A4 | 4 | Control? (bit 0 = don't use the brightness value) |
| 0x200 + n * 0x100 + 0x00 | 4 | Physical address |
| 0x200 + n * 0x100 + 0x04 | 4 | Unknown |
| 0x200 + n * 0x100 + 0x40 | 4 | Pixelformat |
| 0x200 + n * 0x100 + 0x44 | 4 | Height |
| 0x200 + n * 0x100 + 0x48 | 4 | Width |
| 0x200 + n * 0x100 + 0x54 | 4 | Leftover stride |
IftucRegs (control registers?)
| Offset | Size | Description |
|---|---|---|
| 0x10 | 4 | bit 0 = Enable Engine 0 (OLED/LCD) or Engine 1 (HDMI) |