Difference between revisions of "UART Registers"
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| Line 6: | Line 6: | ||
! Size | ! Size | ||
|- | |- | ||
| − | | [[# | + | | [[#SceUartReg_registers|SceUartReg]] |
| 0xE2030000 | | 0xE2030000 | ||
| 0x70000 | | 0x70000 | ||
|- | |- | ||
| − | | SceUartClkgenReg | + | | [[#SceUartClkgenReg_registers|SceUartClkgenReg]] |
| 0xE3105000 | | 0xE3105000 | ||
| 0x1000 | | 0x1000 | ||
| Line 17: | Line 17: | ||
It looks like there are 7 UART devices/ports. The i-th device has its base registers address at <code>SceUartReg + i * 0x10000</code>. | It looks like there are 7 UART devices/ports. The i-th device has its base registers address at <code>SceUartReg + i * 0x10000</code>. | ||
| − | The clock | + | The clock generator configuration for each of these devices is at <code>SceUartClkgenReg + i * 4</code>. |
== SceUartReg registers == | == SceUartReg registers == | ||
| Line 45: | Line 45: | ||
| 6-31 | | 6-31 | ||
| Unused | | Unused | ||
| + | |} | ||
| + | |||
| + | == SceUartClkgenReg registers == | ||
| + | {| class='wikitable' | ||
| + | |- | ||
| + | ! Offset | ||
| + | ! Size | ||
| + | ! Description | ||
| + | |- | ||
| + | | 0x00 | ||
| + | | 4 | ||
| + | | Clock generator for device 0 | ||
| + | |- | ||
| + | | 0x04 | ||
| + | | 4 | ||
| + | | Clock generator for device 1 | ||
| + | |- | ||
| + | | 0x08 | ||
| + | | 4 | ||
| + | | Clock generator for device 2 | ||
| + | |- | ||
| + | | 0x0C | ||
| + | | 4 | ||
| + | | Clock generator for device 3 | ||
| + | |- | ||
| + | | 0x10 | ||
| + | | 4 | ||
| + | | Clock generator for device 4 | ||
| + | |- | ||
| + | | 0x14 | ||
| + | | 4 | ||
| + | | Clock generator for device 5 | ||
| + | |- | ||
| + | | 0x18 | ||
| + | | 4 | ||
| + | | Clock generator for device 6 | ||
|} | |} | ||
Revision as of 07:50, 14 June 2017
MMIO Interfaces
| Name | Physical address | Size |
|---|---|---|
| SceUartReg | 0xE2030000 | 0x70000 |
| SceUartClkgenReg | 0xE3105000 | 0x1000 |
It looks like there are 7 UART devices/ports. The i-th device has its base registers address at SceUartReg + i * 0x10000.
The clock generator configuration for each of these devices is at SceUartClkgenReg + i * 4.
SceUartReg registers
| Offset | Size | Description |
|---|---|---|
| 0x68 | 4 | Read FIFO data available |
| 0x78 | 4 | Read FIFO |
Read FIFO data available
| Bit(s) | Description |
|---|---|
| 0-5 | Number of words available to read |
| 6-31 | Unused |
SceUartClkgenReg registers
| Offset | Size | Description |
|---|---|---|
| 0x00 | 4 | Clock generator for device 0 |
| 0x04 | 4 | Clock generator for device 1 |
| 0x08 | 4 | Clock generator for device 2 |
| 0x0C | 4 | Clock generator for device 3 |
| 0x10 | 4 | Clock generator for device 4 |
| 0x14 | 4 | Clock generator for device 5 |
| 0x18 | 4 | Clock generator for device 6 |