SceKernelIntrMgr: Difference between revisions

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SceKernelIntrMgr is a kernel module that is primary responsible for setting up external and internal interrupts. Notably, it facilitates communication with the [[F00D Processor]].
SceKernelIntrMgr is a kernel module that is primary responsible for setting up external and internal interrupts. Notably, it facilitates communication with the [[Cmep]] processor.


== Module ==
== Module ==
This module exists in both non-secure and secure world. The non-secure world SELF can be found in <code>os0:kd/intrmgr.skprx</code>. It also can be found in the [[Boot Sequence|Boot Image]].
This module exists in both non-secure and secure world. The non-secure world SELF can be found in <code>os0:kd/intrmgr.skprx</code>. It also can be found in the [[Boot Sequence|Boot Image (SKBL)]].


=== Known NIDs ===
{| class="wikitable"
{| class="wikitable"
|-
|-
! Version !! Name !! World !! Privilege !! NID
! Version !! World !! Privilege
|-
|-
| 1.69 || SceKernelIntrMgr || Non-secure || Kernel || 0xB3A12CDC
| 1.69-3.60 || Non-secure || Kernel
|-
|-
| 1.69 || SceKernelIntrMgr || Secure || Kernel || 0x8A9875BC
| 1.69 || Secure || Kernel
|}
|}


Line 22: Line 21:
! Version !! Name !! World !! Visibility !! NID
! Version !! Name !! World !! Visibility !! NID
|-
|-
| 1.69 || [[SceKernelIntrMgr#SceIntrmgrForDriver|SceIntrmgrForDriver]] || Non-secure || Kernel || 0x9DF04041
| 1.69-3.60 || [[SceKernelIntrMgr#SceIntrmgrForDriver|SceIntrmgrForDriver]] || Non-secure || Kernel || 0x9DF04041
|-
| 1.69-3.60 || [[SceKernelIntrMgr#SceIntrmgrForKernel|SceIntrmgrForKernel]] || Non-secure || Kernel || 0x07AC5E3A
|-
| 1.69-1.80 || [[SceKernelIntrMgr#SceIntrmgrForTZS|SceIntrmgrForTZS]]|| Secure || Kernel || 0xEC3056FE
|}
 
== Interrupt ==
 
=== Context ===
 
<source>
PMCNTENCLR <- PMCNTENSET
 
TPIDRPRW <- 0
 
CONTEXTIDR <- 0
TTBR1 <- ?
CONTEXTIDR <- ? (could be restore)
 
DACR <- 0x15450000
 
PMSELR    <- 0
PMXEVTYPER <- unknown
PMXEVCNTR  <- unknown
PMSELR    <- 1
PMXEVTYPER <- unknown
PMXEVCNTR  <- unknown
PMSELR    <- 2
PMXEVTYPER <- unknown
PMXEVCNTR  <- unknown
PMSELR    <- 3
PMXEVTYPER <- unknown
PMXEVCNTR  <- unknown
PMSELR    <- 4
PMXEVTYPER <- unknown
PMXEVCNTR  <- unknown
PMSELR    <- 5
PMXEVTYPER <- unknown
PMXEVCNTR  <- unknown
 
CPACR <- 0xF00000
fpexc <- 0x40000000
 
DBGBVR2 <- unknown
DBGBCR2 <- unknown
DBGBVR3 <- unknown
DBGBCR3 <- unknown
DBGBVR4 <- unknown
DBGBCR4 <- unknown
 
DBGWVR1 <- unknown
DBGWCR1 <- unknown
DBGWVR2 <- unknown
DBGWCR2 <- unknown
DBGWVR3 <- unknown
DBGWCR3 <- unknown
 
TPIDRURO <- 0
</source>
 
== Data segment layout ==
 
{| class="wikitable"
|-
! Static VA !! Offset !! Length !! Description
|-
| 0x81004000 || 0x0 || 0x842F8 || entire
|-
| 0x81004000 || 0x0 || 0x40 * 0x100 || Intr entry info
|-
| 0x81008000 || 0x4000 || 0x80 * 4 || Intr nest info
|-
| 0x81008200 || 0x4200 || 0x80(?) || some memblock/misc info
|-
|-
| 1.69 || [[SceKernelIntrMgr#SceIntrmgrForKernel|SceIntrmgrForKernel]] || Non-secure || Kernel || 0x7AC5E3A
| 0x81008280 || 0x4280 || 0x2000 * 0x10 * 4 || Intr register store area
|-
|-
| 1.69 || [[SceKernelIntrMgr#SceIntrmgrForTZS|SceIntrmgrForTZS]]|| Secure || Kernel || 0xEC3056FE
| 0x81088280 || 0x84280 || 0x78 || Something
|}
|}


== SceIntrmgrForDriver ==
== SceIntrmgrForDriver ==
=== sceKernelIsSubInterruptOccurredForDriver ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0x950B864B
|}
<source lang="C">int sceKernelIsSubInterruptOccurredForDriver(int intr_code, int subinterrupt_code);</source>
=== sceKernelRegisterIntrHandlerForDriver ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0x5C1FEB29
|}
<source lang="c">
typedef struct SceKernelRegisterInterruptOptionsExtended
{
unsigned int size;
unsigned int unk_4;
unsigned int unk_8;
SceKernelIntrOptParam2Callback1 *release_subintr_cb;
SceKernelIntrOptParam2Callback1 *fptr0;
SceKernelIntrOptParam2Callback1 *enable_subintr_cb;
SceKernelIntrOptParam2Callback1 *disable_subintr_cb;
SceKernelIntrOptParam2Callback2 *fptr3;
unsigned int unk_20;
unsigned int unk_24;
} SceKernelRegisterInterruptOptionsExtended; /* size = 0x28 */
typedef struct SceKernelRegisterInterruptOptions
{
unsigned int size;
unsigned int num;
SceKernelRegisterInterruptOptionsExtended *opt2;
unsigned int flags; /* 0b1 = use sensitivity param */
unsigned int sensitivity;
} SceKernelRegisterInterruptOptions; /* size = 0x14 */
typedef int (SceKernelIntrHandler)(int intr_code, void* userCtx);
int sceKernelRegisterIntrHandlerForDriver(int code, const char *name, int interrupt_type, SceKernelIntrHandler *handler, void* userCtx, int priority, int targetcpu, SceKernelRegisterInterruptOptions *opt);
</source>
=== sceKernelReleaseIntrHandlerForDriver ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0xD6009B98
|}
This function first performs a disable and then removes the current interrupt handler associated with the interrupt <code>intr_code</code>.
<source lang="c">int sceKernelReleaseIntrHandlerForDriver(int intr_code);</source>
=== sceKernelDisableIntrForDriver ===
{| class="wikitable"
|-
! Version !! NID
|-
| 0.990-3.60 || 0x180435EC
|}
<source lang="c">int sceKernelDisableIntrForDriver(int intr_code);</source>
This function writes <code>1 << (intr_code % 32)</code> to the Interrupt Disable Registers (offset 0x180 from the Interrupt Distributor registers) at <code> 0x180 + (intr_code / 32) * 4</code>.
=== sceKernelEnableIntrForDriver ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0x7117E827
|}
<source lang="c">int sceKernelEnableIntrForDriver(int intr_code);</source>
This function writes <code>1 << (intr_code % 32)</code> to the Interrupt Enable Registers (offset 0x100 from the Interrupt Distributor registers) at <code> 0x100 + (intr_code / 32) * 4</code>.
=== sceKernelResumeIntrForDriver ===
{| class="wikitable"
|-
! Version !! NID
|-
| 0.990-3.60 || 0xA4C772AF
|}
<source lang="c">int sceKernelResumeIntrForDriver(int intr_code, int enabled);</source>
Enables or disables an interrupt. If a <code>0</code> is passed to <code>enabled</code>, it acts as [[#sceKernelDisableIntrForDriver|sceKernelDisableIntrForDriver]], and if a <code>1</code> is passed, it acts as [[#sceKernelEnableIntrForDriver|sceKernelEnableIntrForDriver]].
=== sceKernelSuspendIntrForDriver ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0x6EC07C56
|}
<source lang="c">int sceKernelSuspendIntrForDriver(int intr_code, SceBool *enabled);</source>
This function returns whether the interrupt <code>intr_code</code> is enabled or not. If it's enabled, a <code>1</code> will be written to <code>enabled</code> and a <code>0</code> otherwise.
To check the enable status, the function checks the bit number <code>intr_code % 32</code> of the Interrupt Enable register (offset 0x100 from the Interrupt Distributor registers) at <code> 0x100 + (intr_code / 32) * 4</code>.
=== sceKernelSetIntrPriorityForDriver ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0x71020E29
|}
<source lang="c">int sceKernelSetIntrPriorityForDriver(int intr_code, unsigned char priority);</source>
This function writes <code>priority</code> to the Interrupt Priority Registers (offset 0x400 from the Interrupt Distributor registers) at <code> 0x400 + intr_code</code>.
=== sceKernelGetIntrPriorityForDriver ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0xE427D050
|}
<source lang="c">int sceKernelGetIntrPriorityForDriver(int intr_code, int *priority);</source>
=== sceKernelSetIntrTargetCpuForDriver ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0x973BACCC
|}
<source lang="c">int sceKernelSetIntrTargetCpuForDriver(int intr_code, int target_cpu);</source>
This function writes the bits 0-8 or 16-24 of <code>target_cpu</code>, depending on whether the mask is in former or the latter bits, to the Interrupt Processor Targets Registers (offset 0x800 from the Interrupt Distributor registers) at <code> 0x800 + intr_code</code>
=== sceKernelGetIntrTargetCpuForDriver ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0x353CFAAE
|}
<source lang="c">int sceKernelGetIntrTargetCpuForDriver(int intr_code, int *cpu_mask);</source>
=== sceKernelGenerateSoftIntrForDriver ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0x29F62500
|}
<source lang="c">int sceKernelGenerateSoftIntrForDriver(int intr_code, unsigned int target_list_filter, unsigned int cpu_target_list);</source>
This function triggers a SGI (software generated interrupt) by writing <code>(target_list_filter << 24) | (cpu_target_list << 16) | intr_code</code> to the Software Generated Interrupt Register (offset 0xF00 from the Interrupt Distributor registers, physical address [[Physical_Memory|0x1A001F00]]).
Note: <code>intr_code</code> must be between <code>0x0</code> and <code>0xF</code>.
=== sceKernelIsIntrContextForDriver ===
{| class="wikitable"
! Version !! NID
|-
| 0.931-3.60 || 0x182EE3E3
|}
Indicates whether or not the thread is currently handling an interrupt.
<source lang="c">SceBool sceKernelIsIntrContextForDriver(void);</source>
Returns <code>SCE_FALSE</code> if the current TPIDRPRW (PL1-only Thread ID Register, holds a pointer to the current ThreadCB) is non-NULL, or if an internal structure field is not set for the current CPU.
=== sceKernelRegisterSubIntrHandlerForDriver ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0x96576C18
|}
<source lang="c">int sceKernelRegisterSubIntrHandlerForDriver(int intr_code, int subintr_code, const char *name, void *handler, void *register_arg);</source>
=== sceKernelReleaseSubIntrHandlerForDriver ===
{| class="wikitable"
|-
! Version !! NID
|-
| 0.990-3.60 || 0x7B9657B3
|}
<source lang="c">int sceKernelReleaseSubIntrHandlerForDriver(int intr_code, int subintr_code);</source>
=== sceKernelCallSubIntrHandlerForDriver ===
{| class="wikitable"
|-
! Version !! NID
|-
| 0.990-3.60 || 0xCC94B294
|}
Triggers a subinterrupt by directly calling it.
<source lang="c">int sceKernelCallSubIntrHandlerForDriver(int intr_code, int subintr_code, void *subintr_arg);</source>
=== sceKernelEnableSubIntrForDriver ===
{| class="wikitable"
|-
! Version !! NID
|-
| 0.990-3.60 || 0x901E41D8
|}
It also calls <code>fptr1</code> of the registered <code>reg_intr_opt2</code> as: <code>reg_intr_opt2.fptr1(intrcode, subintr_code)</code>.
<source lang="c">int sceKernelEnableSubIntrForDriver(unsigned int intrcode, unsigned int subintr_code);</source>
=== sceKernelDisableSubIntrForDriver ===
{| class="wikitable"
|-
! Version !! NID
|-
| 0.990-3.60 || 0x259C6D9E
|}
Calls <code>fptr2</code> of the registered <code>reg_intr_opt2</code> as: <code>reg_intr_opt2.fptr2(intr_code, subintr_code)</code>.
<source lang="c">int sceKernelDisableSubIntrForDriver(int intr_code, int subintr_code);</source>
=== sceKernelSuspendSubIntrForDriver ===
{| class="wikitable"
|-
! Version !! NID
|-
| 0.990-3.60 || 0x3A9EA7D1
|}
Calls <code>fptr3</code> of the registered <code>reg_intr_opt2</code> as: <code>reg_intr_opt2.fptr3(intr_code, subintr_code, arg)</code>.
<source lang="c">int sceKernelSuspendSubIntrForDriver(int intr_code, int subintr_code, void *arg);</source>
=== sceKernelResumeSubIntrForDriver ===
{| class="wikitable"
|-
! Version !! NID
|-
| 0.990-3.60 || 0x957023D0
|}
<source lang="C">int sceKernelResumeSubIntr(int intr_code, int subinterrupt_code, int enabled);</source>
=== sceKernelRegisterIntrHookHandlerForDriver ===
{| class="wikitable"
|-
! Version !! NID
|-
| 0.990-3.60 || 0x99048AEC
|}
<source lang="C">int sceKernelRegisterIntrHookHandler(int intr_code, void *new_handler, void **old_handler);</source>
=== sceKernelReleaseIntrHookHandlerForDriver ===
{| class="wikitable"
|-
! Version !! NID
|-
| 0.990-3.60 || 0xA0B7F44E
|}
<source lang="C">int sceKernelReleaseIntrHookHandler(int intr_code);</source>
=== invoke_callback_842B45DC ===
{| class="wikitable"
|-
! Version !! NID
|-
| 0.990 || not present
|-
| 3.60 || 0xC568F145
|}
invoke callback that was set with 0x842B45DC
<source lang="c">int invoke_callback_842B45DC(int arg1);</source>
== SceIntrmgrForKernel ==
== SceIntrmgrForKernel ==
=== sceKernelEnableCoreIntr_SceIntrmgrForKernel_A60D79A4 ===
{| class="wikitable"
! Version !! NID
|-
| 0.940-3.60 || 0xA60D79A4
|-
| 3.65 || 0xBCD3BB05
|}
Enables interrupts (<code>cpsie i</code>).
<source lang="C">void SceIntrmgrForKernel_A60D79A4(void);</source>
=== sceKernelGetIntrPendingStatusForDebuggerForKernel ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0xA269003D
|}
<source lang="C">int sceKernelGetIntrPendingStatusForDebuggerForKernel(int intr_code);</source>
This function returns whether the interrupt <code>intr_code</code> is pending or not. If it's pending, a <code>1</code> will be returned, and a <code>0</code> will be returned otherwise.
To check the pending status, the function checks the bit number <code>intr_code % 32</code> of the Interrupt Set-Pending Registers (offset 0x200 from the Interrupt Distributor registers) at <code> 0x200 + (intr_code / 32) * 4</code>.
=== sceKernelClearIntrPendingStatusForDebuggerForKernel ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0x4DC48A01
|}
<source lang="C">int sceKernelClearIntrPendingStatusForDebuggerForKernel(int intrcode);</source>
This function writes <code>1 << (intr_code % 32)</code> to the Interrupt Clear-Pending Registers (offset 0x280 from the Interrupt Distributor registers) at <code> 0x280 + (intr_code / 32) * 4</code>.
=== sceKernelAllocSystemCallTableForKernel ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0xB60ACF4B
|-
| 3.65 || 0xB5A665C7
|}
Temp name was sceKernelAllocSyscallTableForKernel.
Calls [[SceSysmem#sceKernelAllocPartitionMemBlockForKernel|sceKernelAllocPartitionMemBlockForKernel]](0x10009, "SceSyscallTable", 0x1020D006, 4 * numSyscalls, 0).
0x10009 is the UID of the "SceKernelRoot" partition.
<source lang="C">
/**
* @brief Allocates the system call table.
*
* @param[in]   numSyscalls    Number of syscalls the allocated table should be able to hold
* @param[in,out] ppTableBase    Pointer to a variable that will recieve the syscall table's base address (must not be NULL)
* @retval (-1) numSyscalls is 0, or the table has already been allocated
* @retval      (<0) Error code
* @retval (>0) UID of the syscall table memory block
*/
SceUID sceKernelAllocSystemCallTableForKernel(SceUInt32 numSyscalls, void** ppTableBase);
</source>
=== sceKernelQueryIntrHandlerInfoForKernel ===
{| class="wikitable"
! Version !! NID
|-
| 0.990-3.60 || 0xB5AFAE49
|}
<source lang="C">int sceKernelQueryIntrHandlerInfoForKernel(unsigned int intr_code, unsigned int a2, int a3);</source>
=== SceIntrmgrForKernel_01E5233E ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0x01E5233E
|}
Copy data to dst from src.
<source lang="C">void SceIntrmgrForKernel_01E5233E(void *dst, const void *src);</source>
=== SceIntrmgrForKernel_37F4627B ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0x37F4627B
|}
Register sceKernelRegisterIntrHandler/sceKernelReleaseIntrHandler exit callback.
<source lang="C">void SceIntrmgrForKernel_37F4627B(void *a1, void *a2);</source>
=== SceIntrmgrForKernel_4F611A63 ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0x4F611A63
|}
Register irq complete callback.
<source lang="C">void SceIntrmgrForKernel_4F611A63(void *a1);</source>
=== SceIntrmgrForKernel_4F890B0C ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0x4F890B0C
|}
Guessed name : sceKernelSetIrqDBGBVRSaveContext
<source lang="C">void SceIntrmgrForKernel_4F890B0C(void *a1);</source>
=== SceIntrmgrForKernel_53DD3BF5 ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0x53DD3BF5
|}
Register irq `setupNextContext_intr` function.
<source lang="C">void SceIntrmgrForKernel_53DD3BF5(void *a1);</source>
=== sceKernelIntrmgrRegisterIntrTraceHookForKernel ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0x6FAC5DEF
|}
<source lang="C">void sceKernelIntrmgrRegisterIntrTraceHookForKernel(void *a1, void *a2);</source>
=== SceIntrmgrForKernel_772BE54F ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0x772BE54F
|}
Register irq `callThreadmgrBeforeIntrHandler` function.
<source lang="C">void SceIntrmgrForKernel_772BE54F(void *a1);</source>
=== SceIntrmgrForKernel_82ADA185 ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0x82ADA185
|}
Register sceKernelTriggerSubIntr's enter/leave callback.
<source lang="C">void SceIntrmgrForKernel_82ADA185(void *a1, void *a2);</source>
=== SceIntrmgrForKernel_842B45DC ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0x842B45DC
|}
Register svc invalid call (?) callback.
<source lang="C">void SceIntrmgrForKernel_842B45DC(void *a1);</source>
=== SceIntrmgrForKernel_89E47181 ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0x89E47181
|}
Guessed name : sceKernelSetIrqDBGWVRSaveContext
<source lang="C">void SceIntrmgrForKernel_89E47181(void *a1);</source>
=== SceIntrmgrForKernel_8ED485C0 ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0x8ED485C0
|}
Like setjmp->longjmp
=== SceIntrmgrForKernel_CAAC949E ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0xCAAC949E
|}
Set 16-bytes to global variable.
<source lang="C">void SceIntrmgrForKernel_CAAC949E(void *a1);</source>
=== sceKernelIntrmgrRegisterSyscallTraceHookForKernel ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0xCE553E9C
|}
<source lang="C">void sceKernelIntrmgrRegisterSyscallTraceHookForKernel(void *a1, void *a2);</source>
=== SceIntrmgrForKernel_EE4CE1DB ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || EE4CE1DB
|}
Like setjmp->setjmp
=== SceIntrmgrForKernel_EF1D3865 ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0xEF1D3865
|}
Return to SceInterruptControllerReg + 0x100 address
<source lang="C">void *SceIntrmgrForKernel_EF1D3865(void);</source>
=== SceIntrmgrForKernel_F281330D ===
{| class="wikitable"
! Version !! NID
|-
| 3.60 || 0xF281330D
|}
Guessed name : sceKernelGetIrqNestCB
<source lang="C">void *SceIntrmgrForKernel_F281330D(SceUInt32 core, SceUInt32 nest);</source>
=== get_intr_logs ===
{| class="wikitable"
! Version !! NID
|-
| 0.990 || 0xB04086C6
|-
| 3.60 || not present
|}
Read [[Physical_Memory#Interrupt_registers]] and writes logs to str_buf.
<source lang="C">int get_intr_logs(char *str_buf, unsigned int max_len);</source>
=== sceKernelPMonSetThreadModeMaskForKernel ===
{| class="wikitable"
! Version !! NID
|-
| 0.990 || 0x730CB409
|-
| 3.60 || not present
|}
<source lang="C">int sceKernelPMonSetThreadModeMaskForKernel(unsigned int mask);</source>
=== sceKernelGetVfpIntRegsAddrForKernel ===
{| class="wikitable"
! Version !! NID
|-
| ? || 0xB2497FBC
|}
== SceIntrmgrForTZS ==
== SceIntrmgrForTZS ==
=== sceKernelUsleepForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931 || 0xC0908EA9
|}
=== sceKernelRegisterMonitorCallHandlerForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931-1.80 || 0xC188114F
|}
Register a SMC (secure only).
<source lang="c">int sceKernelRegisterMonitorCallHandlerForTZS(int smc_id, void **func);</source>
=== sceKernelRegisterIntrHandlerForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931-1.80 || 0x6B84DA8F
|}
<source lang="c">
typedef struct SceKernelRegisterInterruptOptionsExtended { // size is 0x28
unsigned int size;
unsigned int unk_4;
unsigned int unk_8;
SceKernelIntrOptParam2Callback1 *release_subintr_cb;
SceKernelIntrOptParam2Callback1 *fptr0;
SceKernelIntrOptParam2Callback1 *enable_subintr_cb;
SceKernelIntrOptParam2Callback1 *disable_subintr_cb;
SceKernelIntrOptParam2Callback2 *fptr3;
unsigned int unk_20;
unsigned int unk_24;
} SceKernelRegisterInterruptOptionsExtended;
typedef struct SceKernelRegisterInterruptOptions { // size is 0x14
unsigned int size;
unsigned int num;
SceKernelRegisterInterruptOptionsExtended *opt2;
unsigned int flags; /* 0b1 = use sensitivity param */
unsigned int sensitivity;
} SceKernelRegisterInterruptOptions;
typedef int (SceKernelIntrHandler)(int intr_code, void* userCtx);
int sceKernelRegisterIntrHandlerForTZS(int code, const char *name, int interrupt_type, SceKernelIntrHandler *handler, void* userCtx, int priority, int targetcpu, SceKernelRegisterInterruptOptions *pOpt);
</source>
=== sceKernelReleaseIntrHandlerForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931 || 0x75A0F189
|}
=== sceKernelSetIntrPriorityForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931 || 0x9168E78E
|}
=== sceKernelGetIntrPriorityForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931 || 0xFEAC9841
|}
=== sceKernelSetIntrTargetCpuForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931 || 0xAA3C4787
|}
=== sceKernelGetIntrTargetCpuForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931 || 0xF3B92D98
|}
=== sceKernelDisableIntrForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931 || 0x4F39B381
|}
=== sceKernelEnableIntrForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931 || 0x98E38390
|}
=== sceKernelResumeIntrForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931 || 0x92DE2E92
|}
=== sceKernelSuspendIntrForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931 || 0xBFBEAB5C
|}
=== sceKernelIsIntrContextForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931 || 0x636F4549
|}
=== sceKernelGenerateSoftIntrForTZS ===
{| class="wikitable"
! Version !! NID
|-
| 0.931 || 0x28BBA975
|}
<source lang="C">int sceKernelGenerateSoftIntrForTZS(SceUInt32 intr_code, SceUInt32 filter, SceUInt32 target);</source>


== Controller ==
== Controller ==
The interrupt controller is defined in the MPCore TRM [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407i/CACCJFCJ.html]. The PERIPHBASE address (physical) is 0x1A000000.
The interrupt controller is defined in the MPCore TRM [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407i/CACCJFCJ.html]. The PERIPHBASE address (physical) is 0x1A000000.


== Registered Interrupts ==
== Registered Interrupts ==
As specified in [http://www.systems.ethz.ch/sites/default/files/file/aos2012/ReferenceMaterial/InterruptHandling/GIC_architecture_spec_v1_0.pdf GIC Architecture], interrupt 0-15 are software generated interrupts. There are also no private peripheral interrupts (16-31) implemented. Core Handler indicates which core handles the exception. "All" means it can be handled by any core.
 
As specified in [http://www.systems.ethz.ch/sites/default/files/file/aos2012/ReferenceMaterial/InterruptHandling/GIC_architecture_spec_v1_0.pdf the GIC Architecture Specification], interrupt IDs 0 to 15 are reserved for Software Generated Interrupts (SGIs), while interrupt IDs 16 to 31 are reserved for Private Peripheral Interrupts (PPIs). There are no private peripherals on the PS Vita so PPIs are unused.
 
It appears the PS Vita's GIC implements priority bits <code>[7:1]</code> i.e. it only supports 128 priority levels. This means all values in the <code>Priority</code> column should be divided by 2.
 
The <code>Target CPU</code> indicates the CPU(s) the exception can be signaled to - "All" means it can be signaled to any CPU and <code>0x</code>-prefixed values are masks.
 
=== Secure Interrupts ===
 
Those interrupts are marked as Secure using the GIC's ICDISR by SKBL. It also marks interrupts 96-111 as Secure; however, those IDs have never been seen in use. All other interrupts are marked as Non-Secure.
 
{| class="wikitable"
{| class="wikitable"
|-
|-
! Code || World || Registered names || Core Handler || Priority
! Code || Name || Target CPU || Priority || Module
|-
|-
| 0 || Non-secure || ? || 0 || 16
| 11 || ScePervasive || All || 80 || SceDriverTzs
|-
|-
| 1 || Non-secure || ? || 0 || 32
| 33 || SceBusErrorSecure || All || 16 || SceKernelBusError
|-
|-
| 2 || Non-secure || SceThreadmgrSGI || 0 || 48
| 34 || SceEmcTop || All || 80 || SceDriverTzs
|-
|-
| 4 || Non-secure || SceSblSmSchedProxySGI || 0 || 128
| 135 || SceTimerForUsleep || All || 128 || SceKernelIntrMgr
|-
|-
| 6 || Non-secure || SceKernelProcessmgr || 0 || 80
| 200 || SceSblSmSchedCry2Arm0 || 3 || 128 || SceSblSmsched
|-
|-
| 8 || Non-secure || SceDisplayVbStartSGI, SceCtrlVblank || 0 || 160
| 201 || SceSblSmSchedCry2Arm123 || 3 || 128 || SceSblSmsched
|-
|-
| 10 || Non-secure || ScePowerMain || 0 || 80
| 202 || SceSblSmSchedCry2Arm123 || 3 || 128 || SceSblSmsched
|-
|-
| 11 || Secure || ScePervasive || 0 || 80
| 203 || SceSblSmSchedCry2Arm123 || 3 || 128 || SceSblSmsched
|}
 
=== Non-Secure Interrupts ===
 
{| class="wikitable"
|-
|-
| 32 || Non-secure || SceBusError || All || 16
! Code || Name || Target CPU || Priority || Module
|-
|-
| 33 || Secure || SceBusErrorSecure || All || 16
| 0 || SceSDfMgrBreakSgiHandler || 0xF || 16 || [[SceDeci4pSDfMgr]]
|-
|-
| 34 || Secure || SceEmcTop || All || 80
| 1 || SceSDfMgrThreadSgiHandler || 0xF || 32 || [[SceDeci4pSDfMgr]]
|-
|-
| 36 || Non-secure || SceIntrmgrVfpException0 || All || 16
| 2 || SceThreadmgrSGI || 0xF || 48 || [[SceKernelThreadMgr]]
|-
|-
| 37 || Non-secure || SceIntrmgrVfpException1 || All || 16
| 4 || SceSblSmSchedProxySGI || 0xF || 128 || [[SceSblSmschedProxy]]
|-
|-
| 38 || Non-secure || SceIntrmgrVfpException2 || All || 16
| 6 || SceKernelProcessmgr || 0xF || 80 || [[SceProcessmgr]]
|-
|-
| 39 || Non-secure || SceIntrmgrVfpException3 || All || 16
| 7 || SceThreadmgrSGILow || 0xF || 80 || [[SceKernelThreadMgr]]
|-
|-
| 49 || Non-secure || SceGpio1Gate2 || All || 160
| 8 || SceDisplayVbStartSGI || 0xF || 160 || [[SceDisplay]]
|-
|-
| 50 || Non-secure || SceGpio1Gate3 || All || 192
| 10 || ScePowerMain || 0xF || 80 || [[ScePower]]
|-
|-
| 51 || Non-secure || SceGpio1Gate4 || All || 208
| 15 || SceUsbMass || 0xF || 208 || [[SceSdstor]]
|-
|-
| 52 || Non-secure || SceGpuLisr || All || 80
| 32 || SceBusError || 0xF || 16 || [[SceKernelBusError]]
|-
|-
| 56 || Non-secure || SceVipMailbox0 || All || 208
| 36 || SceThreadmgrVfpException0 || 0x1 || 16 || [[SceKernelThreadMgr]]
|-
|-
| 60 || Non-secure || SceMsifIns || All || 128
| 37 || SceThreadmgrVfpException1 || 0x2 || 16 || [[SceKernelThreadMgr]]
|-
|-
| 61 || Non-secure || SceMsifSmshc || All || 128
| 38 || SceThreadmgrVfpException2 || 0x4 || 16 || [[SceKernelThreadMgr]]
|-
|-
| 68 || Non-secure || SceCompat4 || 0 || 160
| 39 || SceThreadmgrVfpException3 || 0x8 || 16 || [[SceKernelThreadMgr]]
|-
|-
| 69 || Non-secure || SceCompat5 || 1 || 160
| 49 || SceGpio1Gate2 || 0xF || 160 || [[SceLowio]]
|-
|-
| 70 || Non-secure || SceCompat6 || 2 || 160
| 50 || SceGpio1Gate3 || 0xF || 192 || [[SceLowio]]
|-
|-
| 71 || Non-secure || SceCompat7 || 0 || 160
| 51 || SceGpio1Gate4 || 0xF || 208 || [[SceLowio]]
|-
|-
| 72 || Non-secure || SceCompat8 || 1 || 160
| 52 || SceGpuLisr || 0xF || 80 || [[SceGpuEs4]]
|-
|-
| 73 || Non-secure || SceCompat9 || 2 || 160
| 60 || SceMsifIns || 0xF || 128 || [[SceMsif]]
|-
|-
| 74 || Non-secure || SceCompat10 || 0 || 160
| 61 || SceMsifSmshc || 0xF || 128 || [[SceMsif]]
|-
|-
| 80 || Non-secure || SceVeneziaMailbox00 || All || 208
| 65 || ? || ? || ? || [[SceCompat]]
|-
|-
| 81 || Non-secure || SceVeneziaMailbox01 || All || 208
| 68 || SceCompat0c || 0x1 || 160 || [[SceCompat]]
|-
|-
| 82 || Non-secure || SceVeneziaMailbox02 || All || 208
| 69 || SceCompat1c || 0x2 || 160 || [[SceCompat]]
|-
|-
| 83 || Non-secure || SceVeneziaMailbox03 || All || 208
| 70 || SceCompat2c || 0x4 || 160 || [[SceCompat]]
|-
|-
| 84 || Non-secure || SceVeneziaMailbox04 || All || 208
| 71 || SceCompat0r || 0x1 || 160 || [[SceCompat]]
|-
|-
| 85 || Non-secure || SceVeneziaMailbox05 || All || 208
| 72 || SceCompat1r || 0x2 || 160 || [[SceCompat]]
|-
|-
| 86 || Non-secure || SceVeneziaMailbox06 || All || 208
| 73 || SceCompat2r || 0x4 || 160 || [[SceCompat]]
|-
|-
| 87 || Non-secure || SceVeneziaMailbox07 || All || 208
| 74 || SceCompatLcdc || 0x1 || 160 || [[SceCompat]]
|-
|-
| 88 || Non-secure || SceVeneziaMailbox08 || All || 208
| 78 || ? || ? || ? || [[SceCompat]]
|-
|-
| 89 || Non-secure || SceVeneziaMailbox09 || All || 208
| 80 || SceVeneziaMailbox00 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 90 || Non-secure || SceVeneziaMailbox10 || All || 208
| 81 || SceVeneziaMailbox01 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 91 || Non-secure || SceVeneziaMailbox11 || All || 208
| 82 || SceVeneziaMailbox02 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 92 || Non-secure || SceVeneziaMailbox12 || All || 208
| 83 || SceVeneziaMailbox03 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 93 || Non-secure || SceVeneziaMailbox13 || All || 208
| 84 || SceVeneziaMailbox04 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 94 || Non-secure || SceVeneziaMailbox14 || All || 208
| 85 || SceVeneziaMailbox05 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 95 || Non-secure || SceVeneziaMailbox15 || All || 208
| 86 || SceVeneziaMailbox06 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 112 || Non-secure || SceDmacmgrDmac0Ch0 || All || 128
| 87 || SceVeneziaMailbox07 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 113 || Non-secure || SceDmacmgrDmac0Ch1 || All || 128
| 88 || SceVeneziaMailbox08 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 114 || Non-secure || SceDmacmgrDmac1Ch0 || All || 128
| 89 || SceVeneziaMailbox09 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 115 || Non-secure || SceDmacmgrDmac1Ch1 || All || 128
| 90 || SceVeneziaMailbox10 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 116 || Non-secure || SceDmacmgrDmac2Ch0 || All || 128
| 91 || SceVeneziaMailbox11 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 117 || Non-secure || SceDmacmgrDmac2Ch1 || All || 128
| 92 || SceVeneziaMailbox12 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 118 || Non-secure || SceDmacmgrDmac3Ch0 || All || 128
| 93 || SceVeneziaMailbox13 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 119 || Non-secure || SceDmacmgrDmac3Ch1 || All || 128
| 94 || SceVeneziaMailbox14 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 120 || Non-secure || SceDmacmgrDmac4Gate0 || 3 || 128
| 95 || SceVeneziaMailbox15 || 0xF || 208 || [[SceCodecEngineWrapper]]
|-
|-
| 121 || Non-secure || SceDmacmgrDmac4Gate1 || 3 || 128
| 112 || SceDmacmgrDmac0Ch0 || 0xF || 128 || [[SceKernelDmacMgr]]
|-
|-
| 122 || Non-secure || SceDmacmgrDmac4Gate2 || 3 || 128
| 113 || SceDmacmgrDmac0Ch1 || 0xF || 128 || [[SceKernelDmacMgr]]
|-
|-
| 123 || Non-secure || SceDmacmgrDmac4Gate3 || 3 || 128
| 114 || SceDmacmgrDmac1Ch0 || 0xF || 128 || [[SceKernelDmacMgr]]
|-
|-
| 124 || Non-secure || SceDmacmgrDmac5Ch0 || All || 128
| 115 || SceDmacmgrDmac1Ch1 || 0xF || 128 || [[SceKernelDmacMgr]]
|-
|-
| 125 || Non-secure || SceDmacmgrDmac5Ch1 || All || 128
| 116 || SceDmacmgrDmac2Ch0 || 0xF || 128 || [[SceKernelDmacMgr]]
|-
|-
| 126 || Non-secure || SceDmacmgrDmac6Ch0 || All || 128
| 117 || SceDmacmgrDmac2Ch1 || 0xF || 128 || [[SceKernelDmacMgr]]
|-
|-
| 127 || Non-secure || SceDmacmgrDmac6Ch1 || All || 128
| 118 || SceDmacmgrDmac3Ch0 || 0xF || 128 || [[SceKernelDmacMgr]]
|-
|-
| 128 || Non-secure || SceSystimerWordTimer0 || All || 128
| 119 || SceDmacmgrDmac3Ch1 || 0xF || 128 || [[SceKernelDmacMgr]]
|-
|-
| 129 || Non-secure || SceSystimerWordTimer1 || All || 128
| 120 || SceDmacmgrDmac4Gate0 || 0x80000 || 128 || [[SceKernelDmacMgr]]
|-
|-
| 130 || Non-secure || SceSystimerWordTimer2 || All || 128
| 121 || SceDmacmgrDmac4Gate1 || 0x80000 || 128 || [[SceKernelDmacMgr]]
|-
|-
| 131 || Non-secure || SceSystimerWordTimer3 || All || 128
| 122 || SceDmacmgrDmac4Gate2 || 0x80000 || 128 || [[SceKernelDmacMgr]]
|-
|-
| 132 || Non-secure || SceSystimerWordTimer4 || All || 128
| 123 || SceDmacmgrDmac4Gate3 || 0x80000 || 128 || [[SceKernelDmacMgr]]
|-
|-
| 133 || Non-secure || SceSystimerWordTimer5 || All || 128
| 124 || SceDmacmgrDmac5Ch0 || 0xF || 128 || [[SceKernelDmacMgr]]
|-
|-
| 134 || Non-secure || SceSystimerWordTimer6 || All || 128
| 125 || SceDmacmgrDmac5Ch1 || 0xF || 128 || [[SceKernelDmacMgr]]
|-
|-
| 135 || Secure || usleep || 2 || 128
| 126 || SceDmacmgrDmac6Ch0 || 0xF || 128 || [[SceKernelDmacMgr]]
|-
|-
| 136 || Non-secure || SceSystimerLongrangeTimer0 || All || 128
| 127 || SceDmacmgrDmac6Ch1 || 0xF || 128 || [[SceKernelDmacMgr]]
|-
|-
| 137 || Non-secure || SceSystimerLongrangeTimer1 || All || 128
| 128 || SceSystimerWordTimer0 || 0xF || 128 || [[SceSystimer]]
|-
|-
| 138 || Non-secure || SceSystimerLongrangeTimer2 || All || 128
| 129 || SceSystimerWordTimer1 || 0xF || 128 || [[SceSystimer]]
|-
|-
| 139 || Non-secure || SceSystimerLongrangeTimer3 || All || 128
| 130 || SceSystimerWordTimer2 || 0xF || 128 || [[SceSystimer]]
|-
|-
| 140 || Non-secure || SceSystimerLongrangeTimer4 || All || 128
| 131 || SceSystimerWordTimer3 || 0xF || 128 || [[SceSystimer]]
|-
|-
| 141 || Non-secure || SceThreadmgrTimer || All || 48
| 132 || SceSystimerWordTimer4 || 0xF || 128 || [[SceSystimer]]
|-
|-
| 142 || Non-secure || SceI2c0 || All || 160
| 133 || SceSystimerWordTimer5 || 0xF || 128 || [[SceSystimer]]
|-
|-
| 143 || Non-secure || SceI2c1 || All || 160
| 134 || SceSystimerWordTimer6 || 0xF || 128 || [[SceSystimer]]
|-
|-
| 145 || Non-secure || ? || All || 160
| 136 || SceSystimerLongrangeTimer0 || 0xF || 128 || [[SceSystimer]]
|-
|-
| 146 || Non-secure || SceUsbEhci0 || All || 160
| 137 || SceSystimerLongrangeTimer1 || 0xF || 128 || [[SceSystimer]]
|-
|-
| 147 || Non-secure || ? || All || 160
| 138 || SceSystimerLongrangeTimer2 || 0xF || 128 || [[SceSystimer]]
|-
|-
| 148 || Non-secure || SceUsbEhci1 || All || 160
| 139 || SceSystimerLongrangeTimer3 || 0xF || 128 || [[SceSystimer]]
|-
|-
| 149 || Non-secure || ? || All || 160
| 140 || SceSystimerLongrangeTimer4 || 0xF || 128 || [[SceSystimer]]
|-
|-
| 150 || Non-secure || SceUsbEhci2 || All || 160
| 141 || SceThreadmgrTimer || 0xF || 48 || [[SceKernelThreadMgr]]
|-
|-
| 151 || Non-secure || SceUdcd1_EP0 || All || 128
| 142 || SceI2c0 || 0xF || 160 || [[SceLowio]]
|-
|-
| 152 || Non-secure || SceUdcd1_EP1-7 || All || 128
| 143 || SceI2c1 || 0xF || 160 || [[SceLowio]]
|-
|-
| 155 || Non-secure || SceUdcd2_EP0 || All || 128
| 145 || SceUsbOhci0 || 0xF || 160 || [[SceUsbd]]
|-
|-
| 156 || Non-secure || SceUdcd2_EP1-7 || All || 128
| 146 || SceUsbEhci0 || 0xF || 160 || [[SceUsbd]]
|-
|-
| 160 || Non-secure || SceCsi0 || All || 160
| 147 || SceUsbOhci1 || 0xF || 160 || [[SceUsbd]]
|-
|-
| 162 || Non-secure || SceCsi1 || All || 160
| 148 || SceUsbEhci1 || 0xF || 160 || [[SceUsbd]]
|-
|-
| 164 || Non-secure || SceUdcd1_phy-ready || All || 128
| 149 || SceUsbOhci2 || 0xF || 160 || [[SceUsbd]]
|-
|-
| 165 || Non-secure || SceUdcd1_vbus || All || 128
| 150 || SceUsbEhci2 || 0xF || 160 || [[SceUsbd]]
|-
|-
| 166 || Non-secure || SceCif0 || All || 160
| 151 || SceUdcd1_EP0 || 0xF || 128 || [[SceUdcd]]
|-
|-
| 168 || Non-secure || SceCif1 || All || 160
| 152 || SceUdcd1_EP1-7 || 0xF || 128 || [[SceUdcd]]
|-
|-
| 170 || Non-secure || SceUdcd2_phy-ready || All || 128
| 155 || SceUdcd2_EP0 || 0xF || 128 || [[SceUdcd]]
|-
|-
| 171 || Non-secure || SceUdcd2_vbus || All || 128
| 156 || SceUdcd2_EP1-7 || 0xF || 128 || [[SceUdcd]]
|-
|-
| 176 || Non-secure || ? || All || 16
| 160 || SceCsi0 || 0xF || 160 || [[SceLowio]]
|-
|-
| 176 || Non-secure || ? || 0 || 16
| 162 || SceCsi1 || 0xF || 160 || [[SceLowio]]
|-
|-
| 177 || Non-secure || ? || 1 || 16
| 164 || SceUdcd1_phy-ready || 0xF || 128 || [[SceUdcd]]
|-
|-
| 178 || Non-secure || ? || 2 || 16
| 165 || SceUdcd1_vbus || 0xF || 128 || [[SceUdcd]]
|-
|-
| 179 || Non-secure || ? || 3 || 16
| 166 || SceCif0 || 0xF || 160 || [[SceLowio]]
|-
|-
| 181 || Non-secure || SceUdcd0_EP0 || All || 128
| 168 || SceCif1 || 0xF || 160 || [[SceLowio]]
|-
|-
| 182 || Non-secure || SceUdcd0_EP1-7 || All || 128
| 170 || SceUdcd2_phy-ready || 0xF || 128 || [[SceUdcd]]
|-
|-
| 184 || Non-secure || ? || All || 128
| 171 || SceUdcd2_vbus || 0xF || 128 || [[SceUdcd]]
|-
|-
| 190 || Non-secure || SceUdcd0_phy-ready || All || 128
| 176 || SceSDbgSdio0Mbox || 0x1 || 16 || [[SceDeci4pSDfMgr]]
|-
|-
| 191 || Non-secure || SceUdcd0_vbus || All || 128
| 177 || SceSDbgSdio0Mbox || 0x2 || 16 || [[SceDeci4pSDfMgr]]
|-
|-
| 193 || Non-secure || ? || 3 || 160
| 178 || SceSDbgSdio0Mbox || 0x4 || 16 || [[SceDeci4pSDfMgr]]
|-
|-
| 194 || Non-secure || SceI2s1 || 3 || 160
| 179 || SceSDbgSdio0Mbox || 0x8 || 16 || [[SceDeci4pSDfMgr]]
|-
|-
| 193 || Non-secure || SceI2s0 || 3 || 160
| 184 || SceDbgSdio1Mbox0 || 0xF || 128 || [[SceDbgSdio]]
|-
|-
| 196 || Non-secure || SceI2s2 || 3 || 160
| 193 || SceI2s0 || 0x80000 || 160 || [[SceAudio]]
|-
|-
| 200 || Secure || SceSblSmSchedCry2Arm0 || 3 || 128
| 194 || SceI2s1 || 0x80000 || 160 || [[SceAudio]]
|-
|-
| 201 || Secure || SceSblSmSchedCry2Arm123 || 3 || 128
| 196 || SceI2s2 || 0x80000 || 160 || [[SceAudio]]
|-
|-
| 202 || Secure || SceSblSmSchedCry2Arm123 || 3 || 128
| 204 || SceIftu0a || 0xF || 80 || [[SceLowio]]
|-
|-
| 203 || Secure || SceSblSmSchedCry2Arm123 || 3 || 128
| 205 || SceIftu0b || 0xF || 80 || [[SceLowio]]
|-
|-
| 204 || Non-secure || SceIftu0a || All || 80
| 206 || SceIftu1a || 0xF || 80 || [[SceLowio]]
|-
|-
| 205 || Non-secure || SceIftu0b || All || 80
| 207 || SceIftu1b || 0xF || 80 || [[SceLowio]]
|-
|-
| 206 || Non-secure || SceIftu1a || All || 80
| 210 || SceDsi1 || 0xF || 160 || [[SceLowio]]
|-
|-
| 207 || Non-secure || SceIftu1b || All || 80
| 213 || SceDsi0 || 0xF || 160 || [[SceLowio]]
|-
|-
| 210 || Non-secure || SceDisplayVbStartHDMI / SceDsi1 || All || 160
| 220 || SceSdif0 || 0xF || 128 || [[SceSdif]]
|-
|-
| 213 || Non-secure || SceDisplayVbStartMainLCD / SceDsi0 || All || 160
| 221 || SceSdif1 || 0xF || 128 || [[SceSdif]]
|-
|-
| 220 || Non-secure || SceSdif0 || All || 128
| 222 || SceSdif2 || 0xF || 128 || [[SceSdif]]
|-
|-
| 221 || Non-secure || SceSdif1 || All || 128
| 225 || SceUart1 || 0x10000 || 80 || [[SceDeci4pSDfCtl]]
|-
|-
| 222 || Non-secure || SceSdif2 || All || 128
| 230 || SceUart6 || 0x10000 || 16 || [[SceDeci4pSCTtyp]]
|-
|-
| 225 || Non-secure || SceUart1 || All || 80
| 244 || SceKernelPaPmoni || 0xF || 208 || [[ScePamgr]]
|-
|-
| 248 || Non-secure || SceGpio0Gate0 || All || 80
| 248 || SceGpio0Gate0 || 0xF || 80 || [[SceLowio]]
|-
|-
| 249 || Non-secure || SceGpio0Gate1 || All || 112
| 249 || SceGpio0Gate1 || 0xF || 112 || [[SceLowio]]
|-
|-
| 250 || Non-secure || SceGpio0Gate2 || All || 160
| 250 || SceGpio0Gate2 || 0xF || 160 || [[SceLowio]]
|-
|-
| 251 || Non-secure || SceGpio0Gate3 || All || 192
| 251 || SceGpio0Gate3 || 0xF || 192 || [[SceLowio]]
|-
|-
| 252 || Non-secure || SceGpio0Gate4 || All || 208
| 252 || SceGpio0Gate4 || 0xF || 208 || [[SceLowio]]
|-
|-
| 253 || Non-secure || SceGpio1Gate0 || All || 80
| 253 || SceGpio1Gate0 || 0xF || 80 || [[SceLowio]]
|-
|-
| 254 || Non-secure || SceGpio1Gate1 || All || 112
| 254 || SceGpio1Gate1 || 0xF || 112 || [[SceLowio]]
|-
| 255 || Non-secure || SceIftu2 || All || 80
|-
|-
| 255 || SceIftu2 || 0xF || 80 || [[SceLowio]]
|}
|}


== Functions ==
== Registered Subinterrupts ==
=== Setting up interrupt ===
 
Non-secure
 
{| class="wikitable"
{| class="wikitable"
|-
|-
! Version
! Interrupt code || Subinterrupt code || Name
! NID
|-
|-
| 1.69 (secure)
| 8 || 2 || SceDispalyVblank
| 0x6B84DA8F
|-
|-
| 1.69 (non-secure)
| 8 || 3 || SceCtrlVblank
| 0x5C1FEB29
|-
|}
| 8 || 5 || SceTouchVblank
<source lang="c">
|-
typedef int(intr_callback)(int code, int unk);
| 8 || 24 || SceHprmVblank
 
|-
typedef struct reg_intr_opt2
| 8 || 25 || SceLedVblank
{
|-
  uint32_t size; //0x28
| 8 || 26 || ScePowerVblank
  uint32_t unk_4;
|-
  uint32_t unk_8;
| 15 || 0 || SceSdstorCardInsert
  uint32_t unk_C;
|-
  intr_callback* fptr0; // function pointer
| 15 || 1 || SceSdstorCardRemove
  intr_callback* fptr1; // function pointer
|-
  intr_callback* fptr2; // function pointer
| 60 || 0 || SceSdstorCardInsert
  uint32_t unk_1C;
|-
  uint32_t unk_20;
| 60 || 1 || SceSdstorCardRemove
  uint32_t unk_24;
|-
}reg_intr_opt2;
| 166 || 0 || SceCif0Camera
 
|-
typedef struct reg_intr_opt
| 168 || 0 || SceCif1Camera
{
  uint32_t size; //0x14
  uint32_t num;
  reg_intr_opt2* opt2;
  uint32_t unk_C;
  uint32_t unk_10;
}reg_intr_opt;
 
typedef int (intr_callback_func)(int unk, void* userCtx);
 
int register_interrupt(int code, const char *name, int interrupt_type, intr_callback_func* func, void* userCtx, int priority, int targetcpu, void *opt);
</source>
 
=== Setting up interrupt,too? ===
{| class="wikitable"
|-
|-
! Version
| 210 || 1 || SceDisplayVbStartHDMI
! NID
|-
|-
| 3.60 (non-secure?)
| 213 || 1 || SceDisplayVbStartMainLCD
| 0x96576C18
|}
<source lang="c">
int register_interrupt2(int intr_code, int unk, const char *name, void *func, int priority?);
</source>
 
=== Enable interrupt? ===
{| class="wikitable"
|-
|-
! Version
| 221 || 0 || SceSdstorCardInsert
! NID
|-
|-
| 3.60 (non-secure?)
| 221 || 1 || SceSdstorCardRemove
| 0x901E41D8
|}
<source lang="c">
int enable_interrupt(int intr_code, int unk);
</source>
 
=== Disable interrupt? ===
{| class="wikitable"
|-
|-
! Version
| 222 || 2 || SceWlanBtRobinWlan
! NID
|-
|-
| 3.60 (non-secure?)
| 222 || 3 || SceBtIntr
| 0x259C6D9E
|}
<source lang="c">
int disable_interrupt(int intr_code, int unk);
</source>
 
=== Registering SMC call (secure only) ===
{| class="wikitable"
|-
|-
! Version
| 248 || 4 || SceSysconCmdclr
! NID
|-
|-
| 1.69 (secure)
| 249 || 13 || SceHdmiIntr
| 0xC188114F
|}
|}
<source lang="c">
int register_smc(int service_id, void **func);
</source>


[[Category:ARM]]
[[Category:Kernel]]
[[Category:Modules]]
[[Category:Modules]]
[[Category:Kernel]]
[[Category:Library]]
[[Category:Devices]]
[[Category:Devices]]

Latest revision as of 05:56, 13 October 2023

SceKernelIntrMgr is a kernel module that is primary responsible for setting up external and internal interrupts. Notably, it facilitates communication with the Cmep processor.

Module

This module exists in both non-secure and secure world. The non-secure world SELF can be found in os0:kd/intrmgr.skprx. It also can be found in the Boot Image (SKBL).

Version World Privilege
1.69-3.60 Non-secure Kernel
1.69 Secure Kernel

Libraries

This module only exports kernel libraries.

Known NIDs

Version Name World Visibility NID
1.69-3.60 SceIntrmgrForDriver Non-secure Kernel 0x9DF04041
1.69-3.60 SceIntrmgrForKernel Non-secure Kernel 0x07AC5E3A
1.69-1.80 SceIntrmgrForTZS Secure Kernel 0xEC3056FE

Interrupt

Context

PMCNTENCLR <- PMCNTENSET

TPIDRPRW <- 0

CONTEXTIDR <- 0
TTBR1 <- ?
CONTEXTIDR <- ? (could be restore)

DACR <- 0x15450000

PMSELR     <- 0
PMXEVTYPER <- unknown
PMXEVCNTR  <- unknown
PMSELR     <- 1
PMXEVTYPER <- unknown
PMXEVCNTR  <- unknown
PMSELR     <- 2
PMXEVTYPER <- unknown
PMXEVCNTR  <- unknown
PMSELR     <- 3
PMXEVTYPER <- unknown
PMXEVCNTR  <- unknown
PMSELR     <- 4
PMXEVTYPER <- unknown
PMXEVCNTR  <- unknown
PMSELR     <- 5
PMXEVTYPER <- unknown
PMXEVCNTR  <- unknown

CPACR <- 0xF00000
fpexc <- 0x40000000

DBGBVR2 <- unknown
DBGBCR2 <- unknown
DBGBVR3 <- unknown
DBGBCR3 <- unknown
DBGBVR4 <- unknown
DBGBCR4 <- unknown

DBGWVR1 <- unknown
DBGWCR1 <- unknown
DBGWVR2 <- unknown
DBGWCR2 <- unknown
DBGWVR3 <- unknown
DBGWCR3 <- unknown

TPIDRURO <- 0

Data segment layout

Static VA Offset Length Description
0x81004000 0x0 0x842F8 entire
0x81004000 0x0 0x40 * 0x100 Intr entry info
0x81008000 0x4000 0x80 * 4 Intr nest info
0x81008200 0x4200 0x80(?) some memblock/misc info
0x81008280 0x4280 0x2000 * 0x10 * 4 Intr register store area
0x81088280 0x84280 0x78 Something

SceIntrmgrForDriver

sceKernelIsSubInterruptOccurredForDriver

Version NID
0.990-3.60 0x950B864B 
int sceKernelIsSubInterruptOccurredForDriver(int intr_code, int subinterrupt_code);

sceKernelRegisterIntrHandlerForDriver

Version NID
0.990-3.60 0x5C1FEB29 
typedef struct SceKernelRegisterInterruptOptionsExtended
{
	unsigned int size;
	unsigned int unk_4;
	unsigned int unk_8;
	SceKernelIntrOptParam2Callback1 *release_subintr_cb;
	SceKernelIntrOptParam2Callback1 *fptr0;
	SceKernelIntrOptParam2Callback1 *enable_subintr_cb;
	SceKernelIntrOptParam2Callback1 *disable_subintr_cb;
	SceKernelIntrOptParam2Callback2 *fptr3;
	unsigned int unk_20;
	unsigned int unk_24;
} SceKernelRegisterInterruptOptionsExtended; /* size = 0x28 */

typedef struct SceKernelRegisterInterruptOptions
{
	unsigned int size;
	unsigned int num;
	SceKernelRegisterInterruptOptionsExtended *opt2;
	unsigned int flags; /* 0b1 = use sensitivity param */
	unsigned int sensitivity;
} SceKernelRegisterInterruptOptions; /* size = 0x14 */

typedef int (SceKernelIntrHandler)(int intr_code, void* userCtx);

int sceKernelRegisterIntrHandlerForDriver(int code, const char *name, int interrupt_type, SceKernelIntrHandler *handler, void* userCtx, int priority, int targetcpu, SceKernelRegisterInterruptOptions *opt);

sceKernelReleaseIntrHandlerForDriver

Version NID
0.990-3.60 0xD6009B98

This function first performs a disable and then removes the current interrupt handler associated with the interrupt intr_code. 

int sceKernelReleaseIntrHandlerForDriver(int intr_code);

sceKernelDisableIntrForDriver

Version NID
0.990-3.60 0x180435EC 
int sceKernelDisableIntrForDriver(int intr_code);

This function writes 1 << (intr_code % 32) to the Interrupt Disable Registers (offset 0x180 from the Interrupt Distributor registers) at 0x180 + (intr_code / 32) * 4.

sceKernelEnableIntrForDriver

Version NID
0.990-3.60 0x7117E827 
int sceKernelEnableIntrForDriver(int intr_code);

This function writes 1 << (intr_code % 32) to the Interrupt Enable Registers (offset 0x100 from the Interrupt Distributor registers) at 0x100 + (intr_code / 32) * 4.

sceKernelResumeIntrForDriver

Version NID
0.990-3.60 0xA4C772AF 
int sceKernelResumeIntrForDriver(int intr_code, int enabled);

Enables or disables an interrupt. If a 0 is passed to enabled, it acts as sceKernelDisableIntrForDriver, and if a 1 is passed, it acts as sceKernelEnableIntrForDriver.

sceKernelSuspendIntrForDriver

Version NID
0.990-3.60 0x6EC07C56 
int sceKernelSuspendIntrForDriver(int intr_code, SceBool *enabled);

This function returns whether the interrupt intr_code is enabled or not. If it's enabled, a 1 will be written to enabled and a 0 otherwise. To check the enable status, the function checks the bit number intr_code % 32 of the Interrupt Enable register (offset 0x100 from the Interrupt Distributor registers) at 0x100 + (intr_code / 32) * 4.

sceKernelSetIntrPriorityForDriver

Version NID
0.990-3.60 0x71020E29 
int sceKernelSetIntrPriorityForDriver(int intr_code, unsigned char priority);

This function writes priority to the Interrupt Priority Registers (offset 0x400 from the Interrupt Distributor registers) at 0x400 + intr_code.

sceKernelGetIntrPriorityForDriver

Version NID
0.990-3.60 0xE427D050 
int sceKernelGetIntrPriorityForDriver(int intr_code, int *priority);

sceKernelSetIntrTargetCpuForDriver

Version NID
0.990-3.60 0x973BACCC 
int sceKernelSetIntrTargetCpuForDriver(int intr_code, int target_cpu);

This function writes the bits 0-8 or 16-24 of target_cpu, depending on whether the mask is in former or the latter bits, to the Interrupt Processor Targets Registers (offset 0x800 from the Interrupt Distributor registers) at 0x800 + intr_code

sceKernelGetIntrTargetCpuForDriver

Version NID
0.990-3.60 0x353CFAAE 
int sceKernelGetIntrTargetCpuForDriver(int intr_code, int *cpu_mask);

sceKernelGenerateSoftIntrForDriver

Version NID
0.990-3.60 0x29F62500 
int sceKernelGenerateSoftIntrForDriver(int intr_code, unsigned int target_list_filter, unsigned int cpu_target_list);

This function triggers a SGI (software generated interrupt) by writing (target_list_filter << 24) | (cpu_target_list << 16) | intr_code to the Software Generated Interrupt Register (offset 0xF00 from the Interrupt Distributor registers, physical address 0x1A001F00). Note: intr_code must be between 0x0 and 0xF.

sceKernelIsIntrContextForDriver

Version NID
0.931-3.60 0x182EE3E3

Indicates whether or not the thread is currently handling an interrupt. 

SceBool sceKernelIsIntrContextForDriver(void);

Returns SCE_FALSE if the current TPIDRPRW (PL1-only Thread ID Register, holds a pointer to the current ThreadCB) is non-NULL, or if an internal structure field is not set for the current CPU.

sceKernelRegisterSubIntrHandlerForDriver

Version NID
0.990-3.60 0x96576C18 
int sceKernelRegisterSubIntrHandlerForDriver(int intr_code, int subintr_code, const char *name, void *handler, void *register_arg);

sceKernelReleaseSubIntrHandlerForDriver

Version NID
0.990-3.60 0x7B9657B3 
int sceKernelReleaseSubIntrHandlerForDriver(int intr_code, int subintr_code);

sceKernelCallSubIntrHandlerForDriver

Version NID
0.990-3.60 0xCC94B294

Triggers a subinterrupt by directly calling it. 

int sceKernelCallSubIntrHandlerForDriver(int intr_code, int subintr_code, void *subintr_arg);

sceKernelEnableSubIntrForDriver

Version NID
0.990-3.60 0x901E41D8

It also calls fptr1 of the registered reg_intr_opt2 as: reg_intr_opt2.fptr1(intrcode, subintr_code). 

int sceKernelEnableSubIntrForDriver(unsigned int intrcode, unsigned int subintr_code);

sceKernelDisableSubIntrForDriver

Version NID
0.990-3.60 0x259C6D9E

Calls fptr2 of the registered reg_intr_opt2 as: reg_intr_opt2.fptr2(intr_code, subintr_code). 

int sceKernelDisableSubIntrForDriver(int intr_code, int subintr_code);

sceKernelSuspendSubIntrForDriver

Version NID
0.990-3.60 0x3A9EA7D1

Calls fptr3 of the registered reg_intr_opt2 as: reg_intr_opt2.fptr3(intr_code, subintr_code, arg). 

int sceKernelSuspendSubIntrForDriver(int intr_code, int subintr_code, void *arg);

sceKernelResumeSubIntrForDriver

Version NID
0.990-3.60 0x957023D0 
int sceKernelResumeSubIntr(int intr_code, int subinterrupt_code, int enabled);

sceKernelRegisterIntrHookHandlerForDriver

Version NID
0.990-3.60 0x99048AEC 
int sceKernelRegisterIntrHookHandler(int intr_code, void *new_handler, void **old_handler);

sceKernelReleaseIntrHookHandlerForDriver

Version NID
0.990-3.60 0xA0B7F44E 
int sceKernelReleaseIntrHookHandler(int intr_code);

invoke_callback_842B45DC

Version NID
0.990 not present
3.60 0xC568F145

invoke callback that was set with 0x842B45DC 

int invoke_callback_842B45DC(int arg1);

SceIntrmgrForKernel

sceKernelEnableCoreIntr_SceIntrmgrForKernel_A60D79A4

Version NID
0.940-3.60 0xA60D79A4
3.65 0xBCD3BB05

Enables interrupts (cpsie i). 

void SceIntrmgrForKernel_A60D79A4(void);

sceKernelGetIntrPendingStatusForDebuggerForKernel

Version NID
0.990-3.60 0xA269003D 
int sceKernelGetIntrPendingStatusForDebuggerForKernel(int intr_code);

This function returns whether the interrupt intr_code is pending or not. If it's pending, a 1 will be returned, and a 0 will be returned otherwise. To check the pending status, the function checks the bit number intr_code % 32 of the Interrupt Set-Pending Registers (offset 0x200 from the Interrupt Distributor registers) at 0x200 + (intr_code / 32) * 4.

sceKernelClearIntrPendingStatusForDebuggerForKernel

Version NID
0.990-3.60 0x4DC48A01 
int sceKernelClearIntrPendingStatusForDebuggerForKernel(int intrcode);

This function writes 1 << (intr_code % 32) to the Interrupt Clear-Pending Registers (offset 0x280 from the Interrupt Distributor registers) at 0x280 + (intr_code / 32) * 4.

sceKernelAllocSystemCallTableForKernel

Version NID
0.990-3.60 0xB60ACF4B
3.65 0xB5A665C7

Temp name was sceKernelAllocSyscallTableForKernel.

Calls sceKernelAllocPartitionMemBlockForKernel(0x10009, "SceSyscallTable", 0x1020D006, 4 * numSyscalls, 0).

0x10009 is the UID of the "SceKernelRoot" partition. 

/**
 * @brief Allocates the system call table.
 *
 * @param[in]	  numSyscalls     Number of syscalls the allocated table should be able to hold
 * @param[in,out] ppTableBase     Pointer to a variable that will recieve the syscall table's base address (must not be NULL)
 * @retval	(-1) numSyscalls is 0, or the table has already been allocated
 * @retval      (<0) Error code
 * @retval	(>0) UID of the syscall table memory block
 */
SceUID sceKernelAllocSystemCallTableForKernel(SceUInt32 numSyscalls, void** ppTableBase);

sceKernelQueryIntrHandlerInfoForKernel

Version NID
0.990-3.60 0xB5AFAE49 
int sceKernelQueryIntrHandlerInfoForKernel(unsigned int intr_code, unsigned int a2, int a3);

SceIntrmgrForKernel_01E5233E

Version NID
3.60 0x01E5233E

Copy data to dst from src. 

void SceIntrmgrForKernel_01E5233E(void *dst, const void *src);

SceIntrmgrForKernel_37F4627B

Version NID
3.60 0x37F4627B

Register sceKernelRegisterIntrHandler/sceKernelReleaseIntrHandler exit callback. 

void SceIntrmgrForKernel_37F4627B(void *a1, void *a2);

SceIntrmgrForKernel_4F611A63

Version NID
3.60 0x4F611A63

Register irq complete callback. 

void SceIntrmgrForKernel_4F611A63(void *a1);

SceIntrmgrForKernel_4F890B0C

Version NID
3.60 0x4F890B0C

Guessed name : sceKernelSetIrqDBGBVRSaveContext 

void SceIntrmgrForKernel_4F890B0C(void *a1);

SceIntrmgrForKernel_53DD3BF5

Version NID
3.60 0x53DD3BF5

Register irq `setupNextContext_intr` function. 

void SceIntrmgrForKernel_53DD3BF5(void *a1);

sceKernelIntrmgrRegisterIntrTraceHookForKernel

Version NID
3.60 0x6FAC5DEF 
void sceKernelIntrmgrRegisterIntrTraceHookForKernel(void *a1, void *a2);

SceIntrmgrForKernel_772BE54F

Version NID
3.60 0x772BE54F

Register irq `callThreadmgrBeforeIntrHandler` function. 

void SceIntrmgrForKernel_772BE54F(void *a1);

SceIntrmgrForKernel_82ADA185

Version NID
3.60 0x82ADA185

Register sceKernelTriggerSubIntr's enter/leave callback. 

void SceIntrmgrForKernel_82ADA185(void *a1, void *a2);

SceIntrmgrForKernel_842B45DC

Version NID
3.60 0x842B45DC

Register svc invalid call (?) callback. 

void SceIntrmgrForKernel_842B45DC(void *a1);

SceIntrmgrForKernel_89E47181

Version NID
3.60 0x89E47181

Guessed name : sceKernelSetIrqDBGWVRSaveContext 

void SceIntrmgrForKernel_89E47181(void *a1);

SceIntrmgrForKernel_8ED485C0

Version NID
3.60 0x8ED485C0

Like setjmp->longjmp

SceIntrmgrForKernel_CAAC949E

Version NID
3.60 0xCAAC949E

Set 16-bytes to global variable. 

void SceIntrmgrForKernel_CAAC949E(void *a1);

sceKernelIntrmgrRegisterSyscallTraceHookForKernel

Version NID
3.60 0xCE553E9C 
void sceKernelIntrmgrRegisterSyscallTraceHookForKernel(void *a1, void *a2);

SceIntrmgrForKernel_EE4CE1DB

Version NID
3.60 EE4CE1DB

Like setjmp->setjmp

SceIntrmgrForKernel_EF1D3865

Version NID
3.60 0xEF1D3865

Return to SceInterruptControllerReg + 0x100 address 

void *SceIntrmgrForKernel_EF1D3865(void);

SceIntrmgrForKernel_F281330D

Version NID
3.60 0xF281330D

Guessed name : sceKernelGetIrqNestCB 

void *SceIntrmgrForKernel_F281330D(SceUInt32 core, SceUInt32 nest);

get_intr_logs

Version NID
0.990 0xB04086C6
3.60 not present

Read Physical_Memory#Interrupt_registers and writes logs to str_buf. 

int get_intr_logs(char *str_buf, unsigned int max_len);

sceKernelPMonSetThreadModeMaskForKernel

Version NID
0.990 0x730CB409
3.60 not present 
int sceKernelPMonSetThreadModeMaskForKernel(unsigned int mask);

sceKernelGetVfpIntRegsAddrForKernel

Version NID
? 0xB2497FBC

SceIntrmgrForTZS

sceKernelUsleepForTZS

Version NID
0.931 0xC0908EA9

sceKernelRegisterMonitorCallHandlerForTZS

Version NID
0.931-1.80 0xC188114F

Register a SMC (secure only). 

int sceKernelRegisterMonitorCallHandlerForTZS(int smc_id, void **func);

sceKernelRegisterIntrHandlerForTZS

Version NID
0.931-1.80 0x6B84DA8F 
typedef struct SceKernelRegisterInterruptOptionsExtended { // size is 0x28
	unsigned int size;
	unsigned int unk_4;
	unsigned int unk_8;
	SceKernelIntrOptParam2Callback1 *release_subintr_cb;
	SceKernelIntrOptParam2Callback1 *fptr0;
	SceKernelIntrOptParam2Callback1 *enable_subintr_cb;
	SceKernelIntrOptParam2Callback1 *disable_subintr_cb;
	SceKernelIntrOptParam2Callback2 *fptr3;
	unsigned int unk_20;
	unsigned int unk_24;
} SceKernelRegisterInterruptOptionsExtended;

typedef struct SceKernelRegisterInterruptOptions { // size is 0x14
	unsigned int size;
	unsigned int num;
	SceKernelRegisterInterruptOptionsExtended *opt2;
	unsigned int flags; /* 0b1 = use sensitivity param */
	unsigned int sensitivity;
} SceKernelRegisterInterruptOptions;

typedef int (SceKernelIntrHandler)(int intr_code, void* userCtx);

int sceKernelRegisterIntrHandlerForTZS(int code, const char *name, int interrupt_type, SceKernelIntrHandler *handler, void* userCtx, int priority, int targetcpu, SceKernelRegisterInterruptOptions *pOpt);

sceKernelReleaseIntrHandlerForTZS

Version NID
0.931 0x75A0F189

sceKernelSetIntrPriorityForTZS

Version NID
0.931 0x9168E78E

sceKernelGetIntrPriorityForTZS

Version NID
0.931 0xFEAC9841

sceKernelSetIntrTargetCpuForTZS

Version NID
0.931 0xAA3C4787

sceKernelGetIntrTargetCpuForTZS

Version NID
0.931 0xF3B92D98

sceKernelDisableIntrForTZS

Version NID
0.931 0x4F39B381

sceKernelEnableIntrForTZS

Version NID
0.931 0x98E38390

sceKernelResumeIntrForTZS

Version NID
0.931 0x92DE2E92

sceKernelSuspendIntrForTZS

Version NID
0.931 0xBFBEAB5C

sceKernelIsIntrContextForTZS

Version NID
0.931 0x636F4549

sceKernelGenerateSoftIntrForTZS

Version NID
0.931 0x28BBA975 
int sceKernelGenerateSoftIntrForTZS(SceUInt32 intr_code, SceUInt32 filter, SceUInt32 target);

Controller

The interrupt controller is defined in the MPCore TRM [1]. The PERIPHBASE address (physical) is 0x1A000000.

Registered Interrupts

As specified in the GIC Architecture Specification, interrupt IDs 0 to 15 are reserved for Software Generated Interrupts (SGIs), while interrupt IDs 16 to 31 are reserved for Private Peripheral Interrupts (PPIs). There are no private peripherals on the PS Vita so PPIs are unused.

It appears the PS Vita's GIC implements priority bits [7:1] i.e. it only supports 128 priority levels. This means all values in the Priority column should be divided by 2.

The Target CPU indicates the CPU(s) the exception can be signaled to - "All" means it can be signaled to any CPU and 0x-prefixed values are masks.

Secure Interrupts

Those interrupts are marked as Secure using the GIC's ICDISR by SKBL. It also marks interrupts 96-111 as Secure; however, those IDs have never been seen in use. All other interrupts are marked as Non-Secure.

Code Name Target CPU Priority Module
11 ScePervasive All 80 SceDriverTzs
33 SceBusErrorSecure All 16 SceKernelBusError
34 SceEmcTop All 80 SceDriverTzs
135 SceTimerForUsleep All 128 SceKernelIntrMgr
200 SceSblSmSchedCry2Arm0 3 128 SceSblSmsched
201 SceSblSmSchedCry2Arm123 3 128 SceSblSmsched
202 SceSblSmSchedCry2Arm123 3 128 SceSblSmsched
203 SceSblSmSchedCry2Arm123 3 128 SceSblSmsched

Non-Secure Interrupts

Code Name Target CPU Priority Module
0 SceSDfMgrBreakSgiHandler 0xF 16 SceDeci4pSDfMgr
1 SceSDfMgrThreadSgiHandler 0xF 32 SceDeci4pSDfMgr
2 SceThreadmgrSGI 0xF 48 SceKernelThreadMgr
4 SceSblSmSchedProxySGI 0xF 128 SceSblSmschedProxy
6 SceKernelProcessmgr 0xF 80 SceProcessmgr
7 SceThreadmgrSGILow 0xF 80 SceKernelThreadMgr
8 SceDisplayVbStartSGI 0xF 160 SceDisplay
10 ScePowerMain 0xF 80 ScePower
15 SceUsbMass 0xF 208 SceSdstor
32 SceBusError 0xF 16 SceKernelBusError
36 SceThreadmgrVfpException0 0x1 16 SceKernelThreadMgr
37 SceThreadmgrVfpException1 0x2 16 SceKernelThreadMgr
38 SceThreadmgrVfpException2 0x4 16 SceKernelThreadMgr
39 SceThreadmgrVfpException3 0x8 16 SceKernelThreadMgr
49 SceGpio1Gate2 0xF 160 SceLowio
50 SceGpio1Gate3 0xF 192 SceLowio
51 SceGpio1Gate4 0xF 208 SceLowio
52 SceGpuLisr 0xF 80 SceGpuEs4
60 SceMsifIns 0xF 128 SceMsif
61 SceMsifSmshc 0xF 128 SceMsif
65 ? ? ? SceCompat
68 SceCompat0c 0x1 160 SceCompat
69 SceCompat1c 0x2 160 SceCompat
70 SceCompat2c 0x4 160 SceCompat
71 SceCompat0r 0x1 160 SceCompat
72 SceCompat1r 0x2 160 SceCompat
73 SceCompat2r 0x4 160 SceCompat
74 SceCompatLcdc 0x1 160 SceCompat
78 ? ? ? SceCompat
80 SceVeneziaMailbox00 0xF 208 SceCodecEngineWrapper
81 SceVeneziaMailbox01 0xF 208 SceCodecEngineWrapper
82 SceVeneziaMailbox02 0xF 208 SceCodecEngineWrapper
83 SceVeneziaMailbox03 0xF 208 SceCodecEngineWrapper
84 SceVeneziaMailbox04 0xF 208 SceCodecEngineWrapper
85 SceVeneziaMailbox05 0xF 208 SceCodecEngineWrapper
86 SceVeneziaMailbox06 0xF 208 SceCodecEngineWrapper
87 SceVeneziaMailbox07 0xF 208 SceCodecEngineWrapper
88 SceVeneziaMailbox08 0xF 208 SceCodecEngineWrapper
89 SceVeneziaMailbox09 0xF 208 SceCodecEngineWrapper
90 SceVeneziaMailbox10 0xF 208 SceCodecEngineWrapper
91 SceVeneziaMailbox11 0xF 208 SceCodecEngineWrapper
92 SceVeneziaMailbox12 0xF 208 SceCodecEngineWrapper
93 SceVeneziaMailbox13 0xF 208 SceCodecEngineWrapper
94 SceVeneziaMailbox14 0xF 208 SceCodecEngineWrapper
95 SceVeneziaMailbox15 0xF 208 SceCodecEngineWrapper
112 SceDmacmgrDmac0Ch0 0xF 128 SceKernelDmacMgr
113 SceDmacmgrDmac0Ch1 0xF 128 SceKernelDmacMgr
114 SceDmacmgrDmac1Ch0 0xF 128 SceKernelDmacMgr
115 SceDmacmgrDmac1Ch1 0xF 128 SceKernelDmacMgr
116 SceDmacmgrDmac2Ch0 0xF 128 SceKernelDmacMgr
117 SceDmacmgrDmac2Ch1 0xF 128 SceKernelDmacMgr
118 SceDmacmgrDmac3Ch0 0xF 128 SceKernelDmacMgr
119 SceDmacmgrDmac3Ch1 0xF 128 SceKernelDmacMgr
120 SceDmacmgrDmac4Gate0 0x80000 128 SceKernelDmacMgr
121 SceDmacmgrDmac4Gate1 0x80000 128 SceKernelDmacMgr
122 SceDmacmgrDmac4Gate2 0x80000 128 SceKernelDmacMgr
123 SceDmacmgrDmac4Gate3 0x80000 128 SceKernelDmacMgr
124 SceDmacmgrDmac5Ch0 0xF 128 SceKernelDmacMgr
125 SceDmacmgrDmac5Ch1 0xF 128 SceKernelDmacMgr
126 SceDmacmgrDmac6Ch0 0xF 128 SceKernelDmacMgr
127 SceDmacmgrDmac6Ch1 0xF 128 SceKernelDmacMgr
128 SceSystimerWordTimer0 0xF 128 SceSystimer
129 SceSystimerWordTimer1 0xF 128 SceSystimer
130 SceSystimerWordTimer2 0xF 128 SceSystimer
131 SceSystimerWordTimer3 0xF 128 SceSystimer
132 SceSystimerWordTimer4 0xF 128 SceSystimer
133 SceSystimerWordTimer5 0xF 128 SceSystimer
134 SceSystimerWordTimer6 0xF 128 SceSystimer
136 SceSystimerLongrangeTimer0 0xF 128 SceSystimer
137 SceSystimerLongrangeTimer1 0xF 128 SceSystimer
138 SceSystimerLongrangeTimer2 0xF 128 SceSystimer
139 SceSystimerLongrangeTimer3 0xF 128 SceSystimer
140 SceSystimerLongrangeTimer4 0xF 128 SceSystimer
141 SceThreadmgrTimer 0xF 48 SceKernelThreadMgr
142 SceI2c0 0xF 160 SceLowio
143 SceI2c1 0xF 160 SceLowio
145 SceUsbOhci0 0xF 160 SceUsbd
146 SceUsbEhci0 0xF 160 SceUsbd
147 SceUsbOhci1 0xF 160 SceUsbd
148 SceUsbEhci1 0xF 160 SceUsbd
149 SceUsbOhci2 0xF 160 SceUsbd
150 SceUsbEhci2 0xF 160 SceUsbd
151 SceUdcd1_EP0 0xF 128 SceUdcd
152 SceUdcd1_EP1-7 0xF 128 SceUdcd
155 SceUdcd2_EP0 0xF 128 SceUdcd
156 SceUdcd2_EP1-7 0xF 128 SceUdcd
160 SceCsi0 0xF 160 SceLowio
162 SceCsi1 0xF 160 SceLowio
164 SceUdcd1_phy-ready 0xF 128 SceUdcd
165 SceUdcd1_vbus 0xF 128 SceUdcd
166 SceCif0 0xF 160 SceLowio
168 SceCif1 0xF 160 SceLowio
170 SceUdcd2_phy-ready 0xF 128 SceUdcd
171 SceUdcd2_vbus 0xF 128 SceUdcd
176 SceSDbgSdio0Mbox 0x1 16 SceDeci4pSDfMgr
177 SceSDbgSdio0Mbox 0x2 16 SceDeci4pSDfMgr
178 SceSDbgSdio0Mbox 0x4 16 SceDeci4pSDfMgr
179 SceSDbgSdio0Mbox 0x8 16 SceDeci4pSDfMgr
184 SceDbgSdio1Mbox0 0xF 128 SceDbgSdio
193 SceI2s0 0x80000 160 SceAudio
194 SceI2s1 0x80000 160 SceAudio
196 SceI2s2 0x80000 160 SceAudio
204 SceIftu0a 0xF 80 SceLowio
205 SceIftu0b 0xF 80 SceLowio
206 SceIftu1a 0xF 80 SceLowio
207 SceIftu1b 0xF 80 SceLowio
210 SceDsi1 0xF 160 SceLowio
213 SceDsi0 0xF 160 SceLowio
220 SceSdif0 0xF 128 SceSdif
221 SceSdif1 0xF 128 SceSdif
222 SceSdif2 0xF 128 SceSdif
225 SceUart1 0x10000 80 SceDeci4pSDfCtl
230 SceUart6 0x10000 16 SceDeci4pSCTtyp
244 SceKernelPaPmoni 0xF 208 ScePamgr
248 SceGpio0Gate0 0xF 80 SceLowio
249 SceGpio0Gate1 0xF 112 SceLowio
250 SceGpio0Gate2 0xF 160 SceLowio
251 SceGpio0Gate3 0xF 192 SceLowio
252 SceGpio0Gate4 0xF 208 SceLowio
253 SceGpio1Gate0 0xF 80 SceLowio
254 SceGpio1Gate1 0xF 112 SceLowio
255 SceIftu2 0xF 80 SceLowio

Registered Subinterrupts

Non-secure

Interrupt code Subinterrupt code Name
8 2 SceDispalyVblank
8 3 SceCtrlVblank
8 5 SceTouchVblank
8 24 SceHprmVblank
8 25 SceLedVblank
8 26 ScePowerVblank
15 0 SceSdstorCardInsert
15 1 SceSdstorCardRemove
60 0 SceSdstorCardInsert
60 1 SceSdstorCardRemove
166 0 SceCif0Camera
168 0 SceCif1Camera
210 1 SceDisplayVbStartHDMI
213 1 SceDisplayVbStartMainLCD
221 0 SceSdstorCardInsert
221 1 SceSdstorCardRemove
222 2 SceWlanBtRobinWlan
222 3 SceBtIntr
248 4 SceSysconCmdclr
249 13 SceHdmiIntr
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