UART Registers: Difference between revisions

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PSVita has 7 UART ports (devices) numbered from 0 to 6. The i-th port has its base registers address at <code>SceUartReg + i * 0x10000</code>. Known ports are listed in [[UART Console]].
The clock generator configuration for each of these ports is at <code>SceUartClkgenReg + i * 4</code>.
== MMIO Interfaces ==
== MMIO Interfaces ==
{| class='wikitable'
{| class='wikitable'
|-
|-
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|}
|}


It looks like there are 7 UART devices/ports. The i-th device has its base registers address at <code>SceUartReg + i * 0x10000</code>.
== SceUartReg registers ==


The clock generator configuration for each of these devices is at <code>SceUartClkgenReg + i * 4</code>.
NOTE: the interface is only 0x80 bytes long, but repeats to fill the 0x10000-byte window allocated to each UART controller.


== SceUartReg registers ==
{| class='wikitable'
{| class='wikitable'
|-
|-
Line 25: Line 29:
! Size
! Size
! Description
! Description
|-
| 0x04
| 4
| Enable port (1 = enable, 0 = disable)
|-
| 0x10
| 4
| ??
|-
| 0x1C
| 4
| ??
|-
| 0x20
| 4
| ??
|-
| 0x28
| 4
| [[#Port status|Port status]]
|-
| 0x30
| 4
| ??
|-
| 0x40
| 4
| ?? A <code>0</code> is written here
|-
| 0x50
| 4
| ??
|-
| 0x54
| 4
| A <code>0x77F</code> is written here after reading from the FIFO
|-
| 0x60
| 4
| ??
|-
| 0x64
| 4
| ?? A <code>0x10001</code> is written here
|-
|-
| 0x68
| 0x68
| 4
| 4
| [[#Read FIFO data available|Read FIFO data available]]
| [[#Read FIFO data available|Read FIFO data available]]
|-
| 0x70
| 4
| Write FIFO
|-
|-
| 0x78
| 0x78
| 4
| 4
| Read FIFO
| Read FIFO
|}
=== Port status ===
{| class="wikitable" border="1"
!  Bit(s)
!  Description
|-
| 8
| Write FIFO not full (0 = full)
|-
| 9
| Port ready (0 = busy)
|}
|}


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== SceUartClkgenReg registers ==
== SceUartClkgenReg registers ==
{| class='wikitable'
{| class='wikitable'
|-
|-
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| 0x00
| 0x00
| 4
| 4
| Clock generator for device 0
| Clock generator for port 0
|-
|-
| 0x04
| 0x04
| 4
| 4
| Clock generator for device 1
| Clock generator for port 1
|-
|-
| 0x08
| 0x08
| 4
| 4
| Clock generator for device 2
| Clock generator for port 2
|-
|-
| 0x0C
| 0x0C
| 4
| 4
| Clock generator for device 3
| Clock generator for port 3
|-
|-
| 0x10
| 0x10
| 4
| 4
| Clock generator for device 4
| Clock generator for port 4
|-
|-
| 0x14
| 0x14
| 4
| 4
| Clock generator for device 5
| Clock generator for port 5
|-
|-
| 0x18
| 0x18
| 4
| 4
| Clock generator for device 6
| Clock generator for port 6
|}
|}
=== Register format ===
{| class="wikitable"
|-
! Bits !! Description
|-
| 31:18
| style="text-align: center" | ''RAZ/WI''
|-
| rowspan="2" | 17:16
| Input clock selection
|-
| 0b00: Off
0b01: 3MHz
0b10: ~12MHz
0b11: ~12MHz (same as 0b10?)
|-
| 15:00 || Prescaler (integer)
|}
NOTE: setting the prescaler to zero stops transmission & reception (i.e., baudrate = 0).
=== Baud rate to SceUartClkgenReg register value ===
Baud rates in ''italic'' indicate the value is approximative (due to the integer prescaler).
{| class='wikitable'
|-
! Baud rate
! Register value
! Notes
|-
| 300
| 0x12710
| 3MHz / 10'000
|-
| 600
| 0x11388
| 3MHz / 5'000
|-
| 1200
| 0x109C4
| 3MHz / 2'500
|-
| 2400
| 0x104E2
| 3MHz / 1'250
|-
| 4800
| 0x10271
| 3MHz / 625
|-
| ''9600''
| 0x10139
| 3MHz / 313
|-
| ''14400''
| 0x100D0
| 3MHz / 208
|-
| ''19200''
| 0x1009C
| 3MHz / 156
|-
| ''28800''
| 0x10068
| 3MHZ / 104
|-
| ''38400''
| 0x1004E
| 3MHz / 78
|-
| ''57600''
| 0x10034
| 3MHz / 52
|-
| ''115200''
| 0x1001A
| 3MHz / 26
|-
| ''230400''
| 0x1000D
| 3MHz / 13
|-
| 250000
| 0x1000C
| 3MHz / 12
|-
| ''460800''
| 0x2001A
| 12MHz / 26
|-
| ''921600''
| 0x2000D
| 12MHz / 13
|-
| 3000000
| 0x10001
| 3MHz
|}
[[Category:MMIO]]

Latest revision as of 18:22, 5 October 2024

PSVita has 7 UART ports (devices) numbered from 0 to 6. The i-th port has its base registers address at SceUartReg + i * 0x10000. Known ports are listed in UART Console.

The clock generator configuration for each of these ports is at SceUartClkgenReg + i * 4.

MMIO Interfaces

Name Physical address Size
SceUartReg 0xE2030000 0x70000
SceUartClkgenReg 0xE3105000 0x1000

SceUartReg registers

NOTE: the interface is only 0x80 bytes long, but repeats to fill the 0x10000-byte window allocated to each UART controller.

Offset Size Description
0x04 4 Enable port (1 = enable, 0 = disable)
0x10 4 ??
0x1C 4 ??
0x20 4 ??
0x28 4 Port status
0x30 4 ??
0x40 4 ?? A 0 is written here
0x50 4 ??
0x54 4 A 0x77F is written here after reading from the FIFO
0x60 4 ??
0x64 4 ?? A 0x10001 is written here
0x68 4 Read FIFO data available
0x70 4 Write FIFO
0x78 4 Read FIFO

Port status

Bit(s) Description
8 Write FIFO not full (0 = full)
9 Port ready (0 = busy)

Read FIFO data available

Bit(s) Description
0-5 Number of words available to read
6-31 Unused

SceUartClkgenReg registers

Offset Size Description
0x00 4 Clock generator for port 0
0x04 4 Clock generator for port 1
0x08 4 Clock generator for port 2
0x0C 4 Clock generator for port 3
0x10 4 Clock generator for port 4
0x14 4 Clock generator for port 5
0x18 4 Clock generator for port 6

Register format

Bits Description
31:18 RAZ/WI
17:16 Input clock selection
0b00: Off

0b01: 3MHz

0b10: ~12MHz

0b11: ~12MHz (same as 0b10?)

15:00 Prescaler (integer)

NOTE: setting the prescaler to zero stops transmission & reception (i.e., baudrate = 0).

Baud rate to SceUartClkgenReg register value

Baud rates in italic indicate the value is approximative (due to the integer prescaler).

Baud rate Register value Notes
300 0x12710 3MHz / 10'000
600 0x11388 3MHz / 5'000
1200 0x109C4 3MHz / 2'500
2400 0x104E2 3MHz / 1'250
4800 0x10271 3MHz / 625
9600 0x10139 3MHz / 313
14400 0x100D0 3MHz / 208
19200 0x1009C 3MHz / 156
28800 0x10068 3MHZ / 104
38400 0x1004E 3MHz / 78
57600 0x10034 3MHz / 52
115200 0x1001A 3MHz / 26
230400 0x1000D 3MHz / 13
250000 0x1000C 3MHz / 12
460800 0x2001A 12MHz / 26
921600 0x2000D 12MHz / 13
3000000 0x10001 3MHz
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