Main Processor: Difference between revisions

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== PL310 L2 Cache ==
== PL310 L2 Cache ==
The Vita uses the [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246f/index.html PL310 r3p1-50rel0] L2 cache (Cache ID Register = 0x410000C7) is is [[Physical Memory|mapped]] to <code>0x1A002000</code>.
 
PSVita uses the [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246f/index.html PL310 r3p1-50rel0] L2 cache (Cache ID Register = 0x410000C7) that is [[Physical Memory|mapped]] to paddr <code>0x1A002000</code>.


=== RO registers ===
=== RO registers ===
{| class='wikitable'
{| class='wikitable'
! Register name !! Value
|-
|-
! Register name
| Cache ID Register || 0x410000c7
! Value
|-
| Cache ID Register
| 0x410000c7
|-
|-
| Cache Type Register
| Cache Type Register || 0x1e440440
| 0x1e440440
|}
|}




[[Category:Devices]]
[[Category:Devices]]

Revision as of 00:20, 18 August 2018

CXD5315GG

See Kermit.

Cortex A9 MPcore

The actual application processor cores are Cortex A9, which is common in modern high performance embedded devices like cell phones and tablets. The Technical Reference Manual gives a good overview of the specific processor features and is a good reference for what ARMv7 implementation specific features are enabled. The Vita cores have a MIDR value of 0x412FC09A, meaning it is Cortex A9 r2p10. Indeed there are usage of undocumented CP15 registers.

Another manual that's important is the MPCore Technical Reference Manual which is specific to the multi-core system the Vita uses. The main information of use are descriptors for the private memory region defined with the PERIPHBASE signal. This is mapped to physical address 0x1A000000.

Identification registers

Register name Value
AIDR 0x00000000
CCSIDR 0x701FE019
CLIDR 0x09200003
CTR 0x83338003
ID_AFR0 0x00000000
ID_DFR0 0x00010444
ID_ISAR0 0x00101111
ID_ISAR1 0x13112111
ID_ISAR2 0x21232041
ID_ISAR3 0x11112131
ID_ISAR4 0x00011142
ID_ISAR5 0x00000000
ID_MMFR0 0x00100103
ID_MMFR1 0x20000000
ID_MMFR2 0x01230000
ID_MMFR3 0x00102111
ID_PFR0 0x00001231
ID_PFR1 0x00000011
MIDR 0x412FC09A
MPIDR 0x80000003
REVIDR 0x412FC09A
TCMTR 0x00000000
TLBTR 0x00000402

Interrupt Controller

As part of the Cortex A9 MPcore, the Vita also implements the Generic Interrupt Controller Architecture. More information on interrupts can be found here.

PL310 L2 Cache

PSVita uses the PL310 r3p1-50rel0 L2 cache (Cache ID Register = 0x410000C7) that is mapped to paddr 0x1A002000.

RO registers

Register name Value
Cache ID Register 0x410000c7
Cache Type Register 0x1e440440