UART Registers

PSVita has 7 UART ports (devices) numbered from 0 to 6. The i-th port has its base registers address at SceUartReg + i * 0x10000. Known ports are listed in UART Console.

The clock generator configuration for each of these ports is at SceUartClkgenReg + i * 4.

MMIO Interfaces

Name	Physical address	Size
SceUartReg	0xE2030000	0x70000
SceUartClkgenReg	0xE3105000	0x1000

SceUartReg registers

NOTE: the interface is only 0x80 bytes long, but repeats to fill the 0x10000-byte window allocated to each UART controller.

Offset	Size	Description
0x04	4	Enable port (1 = enable, 0 = disable)
0x10	4	??
0x1C	4	??
0x20	4	??
0x28	4	Port status
0x30	4	??
0x40	4	?? A 0 is written here
0x50	4	??
0x54	4	A 0x77F is written here after reading from the FIFO
0x60	4	??
0x64	4	?? A 0x10001 is written here
0x68	4	Read FIFO data available
0x70	4	Write FIFO
0x78	4	Read FIFO

Port status

Bit(s)	Description
8	Write FIFO not full (0 = full)
9	Port ready (0 = busy)

Read FIFO data available

Bit(s)	Description
0-5	Number of words available to read
6-31	Unused

SceUartClkgenReg registers

Offset	Size	Description
0x00	4	Clock generator for port 0
0x04	4	Clock generator for port 1
0x08	4	Clock generator for port 2
0x0C	4	Clock generator for port 3
0x10	4	Clock generator for port 4
0x14	4	Clock generator for port 5
0x18	4	Clock generator for port 6

Baud rate to SceUartClkgenReg register value

Baud rate	Register value
300	0x12710
600	0x11388
1200	0x109C4
2400	0x104E2
4800	0x10271
9600	0x10139
14400	0x100D0
19200	0x1009C
28800	0x10068
38400	0x1004E
57600	0x10034
115200	0x1001A
230400	0x1000D
250000	0x1000C
460800	0x2001A
921600	0x2000D
3000000	0x10001