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• I2C Registers
  {| class="wikitable" border="1" | 1
  1 KB (181 words) - 21:03, 10 January 2024
• DSI Registers
  | bits[1:0]: Video mode (0 = Progressive, 0b11 = Interlaced) | bits[31:0]: <code>(htotal * clocks_per_pixel) >> 1</code>
  3 KB (442 words) - 10:27, 2 November 2019
• Caches
  Tag Latency Control Register is set to <1, 1, 1> (writes 0 to the L2 register), and Tag Latency Control Register to <2, 4, | 1
  1 KB (194 words) - 07:38, 13 January 2024
• MSIF Registers
  | 1 | Port 1 I/O request address
  1 KB (175 words) - 17:48, 9 November 2019
• GPIO Registers
  | Port mode (1=out, 0=in) (1 bit each port) | Port read (0=low, 1=high) (1 bit each port)
  3 KB (449 words) - 18:25, 27 September 2022
• PSP Emulator
  | Interrupt pending and ack/clear, 1 bit each | Interrupt enable/mask, 1 bit each
  2 KB (281 words) - 10:04, 14 April 2020
• Cmep basics
  * $1 = arg0 * DIV = 1: 32-bit divide instruction on
  3 KB (481 words) - 06:59, 10 September 2023
• SPI Registers
  | Start transfer (bit 0 or 1), transfer direction (bit 0 or 1)?
  1 KB (159 words) - 13:56, 29 May 2021
• UART Registers
  | Enable port (1 = enable, 0 = disable) {| class="wikitable" border="1"
  2 KB (297 words) - 22:00, 1 May 2023
• PSM
  sceKernelUnlockMutex (*mutex, 1); sceKernelLockMutex (*mutex, 1, 0);
  3 KB (349 words) - 15:27, 23 September 2017
• Act.dat
  | Version || 0x4 || 0x4 || 00000001, 00000002 || 1(old) or 2(current) | Unknown3 || 0x860 || 0x10 || N.A|| Encrypted_data for v.1 / Padding for v.2
  1 KB (180 words) - 22:09, 1 May 2023
• ARZL
  1) Apply ARM filter. See [[#ARM Filter]]. At least 1 byte of data is required. 0 byte data cannot be encoded.
  7 KB (924 words) - 07:50, 13 January 2024
• SceError
  | 1.69-3.60 || Non-secure || Kernel | 1.69 || [[SceError#SceErrorForDriver|SceErrorForDriver]] || Non-secure || Ker
  10 KB (983 words) - 21:01, 1 May 2023
• UDC
  | 1 | Same net as pin 1
  3 KB (436 words) - 13:56, 29 March 2024
• Cookie
  | 1 | Net 1 (Battery)
  2 KB (402 words) - 20:40, 6 January 2024
• TrustZone
  // Step 1: Change the processor mode to Monitor Mode scr = ReadCPReg(base, 15, 0, 1, 1, 0);
  6 KB (860 words) - 00:18, 19 January 2024
• SceSysconTzs
  sceKernelRegisterMonitorCallHandler(0x11a, FUN_81000184 + 1);
  461 bytes (48 words) - 23:38, 31 March 2024
• External Boot Mode
  # Only state 1 handles flag <code>0x18</code>. # Main Function in state 1 is called with target state 9. It does some unknown tasks (maybe power on d
  3 KB (471 words) - 21:13, 6 January 2024
• Secure Modules
  * syscall 1: Unload * while(1) sleep()
  3 KB (398 words) - 19:17, 20 September 2023
• IFTU Registers
  ...www.telecomarchive.com/docs/bsp-archive/365/365-353-011_I2.pdf] at chapter 1.2.7.2 Facility Terminating Unit and Integrated | CRTC mask: bit 0 = enable scanout to engine/CRTC of OLED/LCD, bit 1 = enable scanout to engine/CRTC of HDMI
  6 KB (863 words) - 23:49, 6 January 2022

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