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| Cortex A9 SMP ROM Table | DBG0 (Cortex A9)

== Cortex A9 MPcore == ...a cores have a MIDR value of <code>0x412FC09A</code>, meaning it is Cortex-A9 r2p10. Indeed there are usage of undocumented CP15 registers.

...s originating from ARM Secure state or Non-Secure state because ARM Cortex-A9 processors with Security Extensions have [https://developer.arm.com/documen

...pic/com.arm.doc.ddi0407i/DDI0407I_cortex_a9_mpcore_r4p1_trm.pdf ARM Cortex A9 MPcore]. It implements ARM TrustZone for execution in both a non-secure wor

| ES1 || ??? || DEM revision before DEM-3000G || CPU is Cortex-A8, GPU is SGX541MP, ?no CDRAM?. Has two minor revisions: ES1.0 and ES1.1. | ES2 || ??? || DEM-3000G? to DEM-3000H? || CPU is Cortex-A9, GPU is SGX543MP4+. Has only one minor revision: ES2.0. Has 2 banks of LPDD

...at secure devices such as [[Cmep]] use FIQs to communicate with the Cortex A9 cores. See [[SceKernelIntrMgr]]. ...ferred to the next exception handler in chain. According to the ARM Cortex-A9 TRM, this MCRR instruction is used to program the ''Preload Engine'' channe

| ARM Cortex-A9 Debug ROM Table