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# Map SceCrashDumpZero to start of DRAM at PA 0x40000000 # Configure SceDmac5Reg and loop through all of DRAM at PA 0x40200000 in 0x10000 byte chunks

#define READAS_DEV_UNK 0b10 // masks DRAM and DRAM regs, from ARM bus

...nto DRAM and resets the ARM CPU. The stage at this point would have set up DRAM and the [[eMMC]] driver. There is no Virtual Memory Addressing at this poin ...ake effect. The other TrustZone modules are loaded, then the [[TrustZone]] DRAM region (0x40000000-0x40300000 on FW 1.69, 0x40200000 on later firmwares ?wh

As TrustZone resides in the same DRAM as Non-secure World, it could be read from Non-secure World. To prevent tha ...a list of known devices that can only be accessed in the Secure World. The DRAM region <code>0x40000000</code> for 2MB (3MB prior to System Software versio

* Non-secure DRAM (starting at 0x40200000). Note: this is weird because if configuration (wor

...as the "main memory"). The retail unit and TestKit carry 512 MiB of LPDDR2 DRAM. == LPDDR2 DRAM (main memory) ==

Syscon powers up and sets up DRAM, sets up boot context buffer, turns on the [[Kermit|KERMIT SOC]] which even ...d prog_rvk.srvk read from the eMMC [[SLB2]] partition are both loaded into DRAM. Finally, the [[Second Loader]] resets itself with a pointer to the secure_

A 2Gb (256MiB) MDDR DRAM chip manufactured by Samsung. ...(A) can load Miniboot (B) or decrypt and execute a blob already present in DRAM, but we will ignore code related to this and focus on the intresting parts

| 512MiB DRAM. | 1GiB DRAM for Development Kit.

...w power state where the main application processor is turned off. The main DRAM state is preserved so upon resume, the kernel does not have to be reloaded. ...nd belong in a specific range of physical address space (namely Non-Secure DRAM). If the check fails, SKBL enters an infinite loop and the boot process hal

...o SKBL text segment base address. See [[Physical_Memory#Secure_DRAM|Secure DRAM]].

| 0x90 || Secure || [[Pervasive#DRAM Main Clock|DRAM Main Clock]] | 0x94 || Secure || [[Pervasive#DRAM Sub Clock|DRAM Sub Clock]]

# DRAM for CP. 256MB. Labeled "Samsung K4X2G323PC-8GD8"

...ty, signature, format, etc) and decrypts the data directly into the shared DRAM. After clearing the cache, the non-secure kernel has access to the data. Cm

| 0x60 || 0x4 || second_loader || DRAM base paddr (0x40000000) | 0x64 || 0x4 || second_loader || DRAM size (0x20000000 on retail and testkit, 0x40000000 on DevKit in DevKit Memo

| 0x513 || 0x18000001 || 0x18000003 || Y || second_loader || DRAM size. Set to 0x20000000 by default, 0x40000000 on DevKit in DevKit Memory S

...etermined from bit 7 of boot_type returned by syscon. Then, something with dram??? If boot type is resume but TZ magic word (0x9E3199B7) isn't present, it

| Debug PA Dram kernel mapping. If you have dipsw 0xD4, This is mapped.

.... If that is the case, the module is loaded into DevKit Additional Memory (DRAM).

...ng material is a cmep payload that is constantly updating a CTR counter in DRAM. cmep state is verified by checking if this CTR counter is updated.