Search results

• SceProcessmgr
  [[Category:ARM]]
  55 KB (6,358 words) - 05:12, 13 February 2024
• ScePower
  Arm : 333 [[Category:ARM]]
  35 KB (3,539 words) - 19:42, 25 March 2024
• SceGpuEs4User
  [[Category:ARM]]
  579 bytes (60 words) - 21:03, 1 May 2023
• SceSblMgKeyMgr
  [[Category:ARM]]
  1 KB (144 words) - 21:28, 1 May 2023
• Secure Modules
  ...ions is called by the [[Second Loader]], the [[Kernel Boot Loader]] or the ARM [[Kernel]], and unloaded after the call.
  3 KB (398 words) - 19:17, 20 September 2023
• Sysroot
  Sysroot is a structure for low-level access created when ARM KBL and Kernel are started. Many are pointers to functions or structures th
  211 bytes (34 words) - 05:18, 1 May 2023
• SceSblFirstImageWriter
  [[Category:ARM]]
  6 KB (592 words) - 21:27, 1 May 2023
• SceIdStorage
  [[Category:ARM]]
  10 KB (1,100 words) - 21:04, 1 May 2023
• SceNetPs
  [[Category:ARM]]
  11 KB (1,445 words) - 21:21, 1 May 2023
• Boot Sequence
  ...DI0407I_cortex_a9_mpcore_r4p1_trm.pdf ARM Cortex A9 MPcore]. It implements ARM TrustZone for execution in both a non-secure world and a sandboxed [[TrustZ The [[Cmep|cmep processor]] is the actual secure boot device rather than the ARM processor. The cmep processor's boot ROM, nicknamed [[First Loader]], is th
  12 KB (1,757 words) - 08:24, 9 August 2023
• SceCodecEngineWrapper
  [[Category:ARM]]
  12 KB (1,176 words) - 10:07, 25 August 2023
• SceSysconTzs
  [[Category:ARM]]
  461 bytes (48 words) - 23:38, 31 March 2024
• SceVeneziaImage
  This module doesn't contain any ARM code; instead, it holds the image for execution on the VENEZIA coprocessor. MeP code parses RPC calls from ARM (issued with <code>sceVeneziaRpcCallGenericThunk()</code> in a function at
  5 KB (845 words) - 21:40, 1 May 2023
• SceSblPcffBin
  [[Category:ARM]]
  385 bytes (56 words) - 05:25, 18 January 2024
• SceIofilemgr
  [[Category:ARM]]
  71 KB (8,747 words) - 13:51, 13 November 2023
• SceSqliteVsh
  [[Category:ARM]]
  7 KB (875 words) - 23:07, 31 March 2024
• SceAVConfig
  [[Category:ARM]]
  3 KB (249 words) - 20:37, 1 May 2023
• SceKernelBootimage
  [[Category:ARM]]
  2 KB (372 words) - 21:05, 1 May 2023
• SceUsbMass
  [[Category:ARM]]
  3 KB (299 words) - 21:38, 1 May 2023
• SceLibDeflt
  [[Category:ARM]]
  933 bytes (91 words) - 00:22, 1 April 2024
• SceDeci4pDtracep
  [[Category:ARM]]
  102 bytes (12 words) - 20:56, 1 May 2023
• SceKernelBusError
  [[Category:ARM]]
  848 bytes (93 words) - 00:19, 1 April 2024
• SceLowio
  Requests ARM [[TrustZone]] using [[SMC]] 0x114. [[Category:ARM]]
  56 KB (6,898 words) - 22:15, 5 February 2024
• SceError
  [[Category:ARM]]
  10 KB (983 words) - 21:01, 1 May 2023
• SceAvcodecUser
  [[Category:ARM]]
  8 KB (646 words) - 20:46, 1 May 2023
• SceMagicGate
  [[Category:ARM]]
  3 KB (334 words) - 00:04, 1 April 2024
• SceKernelSSProxy
  [[Category:ARM]]
  3 KB (308 words) - 21:07, 1 May 2023
• SceUsbstorMg
  [[Category:ARM]]
  145 bytes (21 words) - 21:39, 1 May 2023
• Memory System
  Any device connected to the memory system, such as ARM cores, DMA controllers, LPDDR2... A module that can initiate read and write requests to the interconnect (e.g. ARM cores, DMA, ...).
  9 KB (1,367 words) - 17:27, 25 November 2023
• SceCtrl
  [[Category:ARM]]
  13 KB (1,337 words) - 11:44, 7 June 2023
• SceWlanBt
  [[Category:ARM]]
  2 KB (160 words) - 21:43, 1 May 2023
• Security
  ....self does not itself run on cmep but only contains encrypted segments for ARM to run. Unless indicated otherwise, all processes are encrypted and require === ARM Secure Kernel ===
  6 KB (1,004 words) - 08:27, 4 August 2023
• SceDeci4pDbgp
  @param[in] arm_opcode - Opcode of the ARM instruction that triggered breakpoint (reversed endianness) @param[in] arm_opcode - Opcode of the ARM instruction that triggered breakpoint (reversed endianness)
  5 KB (642 words) - 13:11, 9 June 2023
• SceKernelPsp2Config
  [[Category:ARM]]
  965 bytes (112 words) - 21:06, 1 May 2023
• SceMemDisk
  [[Category:ARM]]
  1 KB (171 words) - 21:19, 1 May 2023
• SceCommonGuiDialog
  [[Category:ARM]]
  5 KB (534 words) - 16:00, 30 March 2024
• SceKernelIntrMgr
  ...ler is defined in the MPCore TRM [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407i/CACCJFCJ.html]. The PERIPHBASE address (physical) is 0x1A00000 [[Category:ARM]]
  30 KB (3,151 words) - 05:56, 13 October 2023
• SceActivityDb
  [[Category:ARM]]
  4 KB (491 words) - 20:38, 1 May 2023
• SceCoredump
  [[Category:ARM]]
  8 KB (921 words) - 13:57, 9 June 2023
• ScePromoterUtil
  [[Category:ARM]]
  4 KB (515 words) - 21:24, 1 May 2023
• SceDrmPsmKdc
  [[Category:ARM]]
  1 KB (148 words) - 00:31, 1 April 2024
• SceSamantha
  [[Category:ARM]]
  3 KB (362 words) - 00:12, 1 April 2024
• SceDeci4pPamp
  [[Category:ARM]]
  127 bytes (14 words) - 20:56, 1 May 2023
• SceSystimer
  [[Category:ARM]]
  6 KB (725 words) - 18:04, 11 August 2023
• SceHdmi
  [[Category:ARM]]
  4 KB (486 words) - 21:03, 1 May 2023
• SceUsbd
  [[Category:ARM]]
  7 KB (710 words) - 21:39, 1 May 2023
• SceLibft2
  [[Category:ARM]]
  16 KB (2,040 words) - 09:11, 10 July 2023
• SceWebCore
  [[Category:ARM]]
  290 bytes (41 words) - 21:43, 1 May 2023
• Cmep registers
  The mailbox is used for communication between ARM [[TrustZone]] and [[Cmep]] ([[Second Loader]] and [[Secure Kernel]]), and w ...t by Cmep to ARM [[TrustZone]] using the lower 16-bits at 0xE0000000. When ARM [[TrustZone]] has read it, the register is set to 0.
  18 KB (2,382 words) - 02:14, 27 October 2023
• SceMgVideo
  [[Category:ARM]]
  3 KB (410 words) - 13:11, 18 September 2023

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