Search results
Jump to navigation
Jump to search
- [[Category:ARM]]102 bytes (10 words) - 21:21, 1 May 2023
- ...kernel. However, this timer's MMIO range is not blacklisted from access by ARM cores in Non-Secure state. An attacker in Non-Secure state can thus change ...and P correspond to the relocation variables detailed in the "ELF for the Arm® Architecture" document.23 KB (3,419 words) - 11:41, 8 February 2024
- 2: DD2 (VDDA - ARM core, L2 cache) SetArmClockFrequency Finalize Syscon update by sending checksum from ARM to Syscon.110 KB (12,775 words) - 21:59, 4 April 2024
- [[Category:ARM]]2 KB (238 words) - 12:03, 10 January 2024
- [[Category:ARM]]1,000 bytes (100 words) - 21:19, 1 May 2023
- The UART0 is a debugging console used by ARM, cMep and Syscon. The logic level is 1.8V.2 KB (333 words) - 21:41, 11 September 2022
- [[Category:ARM]]520 bytes (69 words) - 20:54, 1 May 2023
- #define READAS_DEV_UNK 0b10 // masks DRAM and DRAM regs, from ARM bus3 KB (537 words) - 21:58, 1 May 2023
- ...er value for MIPS, TOC address (address of .toc) for PowerPC, always 0 for ARM. | Offset to top of ARM EXIDX (optional)38 KB (5,257 words) - 14:21, 25 December 2023
- [[Category:ARM]]71 KB (8,747 words) - 13:51, 13 November 2023
- [[Category:ARM]]6 KB (637 words) - 15:50, 22 January 2024
- [[Category:ARM]]5 KB (469 words) - 01:16, 9 August 2023
- [[Category:ARM]]27 KB (3,421 words) - 21:04, 21 January 2024
- [[Category:ARM]]1 KB (71 words) - 22:56, 31 March 2024
- [[Category:ARM]]2 KB (167 words) - 20:54, 1 May 2023
- [[Category:ARM]]271 bytes (40 words) - 21:35, 1 May 2023
- [[Category:ARM]]522 bytes (79 words) - 20:57, 1 May 2023
- |group4 = ARM side basic1 KB (122 words) - 06:06, 15 August 2023
- [[Category:ARM]]6 KB (817 words) - 23:37, 31 March 2024
- [[Category:ARM]]278 bytes (27 words) - 21:02, 1 May 2023