Main Processor

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Main SoC

See Kermit.

Cortex A9 MPcore

The custom SoC includes the ARM Cortex-A9 MPCore as its CPU, mounting four little-endian ARM Cortex-A9 processor cores, which is common in modern high performance embedded devices like cell phones and tablets. The PSVita cores have a MIDR value of 0x412FC09A, meaning it is Cortex-A9 r2p10. Indeed there are usage of undocumented CP15 registers.

Each core includes the following features:

  • L1 Instruction Cache of 32 KiB and Data Cache of 32 KiB
  • Media Processing Engine (MPE) that can execute Advanced SIMD instructions (NEONv1) and Vector Floating-Point v3 instructions (VFPv3)

In addition, there is a L2 cache of 2 MiB shared by all cores, while precisely speaking, it's external to the ARM processor core.


A lot of useful information is available about ARM (Advanced RISC Machines) on the internet including ARM Ltd. official site.

  • Refer to the following document for the instruction set, memory model and programmers' model: ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition.
  • Cortex-A9 Technical Reference Manual

(corresponding to the chip revision supposed to be included in DevKit):

  • Cortex-A9 NEON Media Processing Engine Technical Reference Manual

(NEON: Advanced SIMD instructions)

  • Cortex-A9 NEON MPE > VFPv3 architecture hardware support

(The above reference destination has been confirmed as of June 26, 2014. Note that pages may have been subsequently moved or its contents modified.)

Identification registers

Register name Value
AIDR 0x00000000
CCSIDR 0x701FE019
CLIDR 0x09200003
CTR 0x83338003
ID_AFR0 0x00000000
ID_DFR0 0x00010444
ID_ISAR0 0x00101111
ID_ISAR1 0x13112111
ID_ISAR2 0x21232041
ID_ISAR3 0x11112131
ID_ISAR4 0x00011142
ID_ISAR5 0x00000000
ID_MMFR0 0x00100103
ID_MMFR1 0x20000000
ID_MMFR2 0x01230000
ID_MMFR3 0x00102111
ID_PFR0 0x00001231
ID_PFR1 0x00000011
MIDR 0x412FC09A
MPIDR 0x80000003
TCMTR 0x00000000
TLBTR 0x00000402

Interrupt Controller

As part of the Cortex A9 MPcore, the Vita also implements the Generic Interrupt Controller Architecture. More information on interrupts can be found here.

L2 Cache

PSVita uses the PL310 r3p1-50rel0 L2 cache (Cache ID Register = 0x410000C7) that is mapped to paddr 0x1A002000.

RO registers

Register name Value
Cache ID Register 0x410000c7
Cache Type Register 0x1e440440