User contributions
Jump to navigation
Jump to search
- 23:32, 15 July 2017 diff hist +80 SceExcpmgr →SMC calls
- 23:24, 15 July 2017 diff hist +192 SceExcpmgr →SMC calls
- 23:20, 15 July 2017 diff hist +3 Pervasive →Devices
- 22:43, 15 July 2017 diff hist +3 ScePower →scePowerSetGpuClockFrequency
- 22:42, 15 July 2017 diff hist +22 ScePower →scePowerSetGpuClockFrequency
- 17:51, 15 July 2017 diff hist +130 SceExcpmgr →SMC calls
- 17:49, 15 July 2017 diff hist +83 SceExcpmgr →SMC calls
- 16:51, 15 July 2017 diff hist +137 SceExcpmgr →SMC calls
- 16:49, 15 July 2017 diff hist +179 SceSysmem →SceCpuForKernel
- 15:51, 15 July 2017 diff hist +283 SceExcpmgr →SMC calls
- 13:22, 15 July 2017 diff hist +8 SceExcpmgr →SMC calls
- 13:21, 15 July 2017 diff hist +37 SceExcpmgr →SMC calls
- 08:51, 15 July 2017 diff hist +34 SceKernelIntrMgr →Setting up interrupt
- 08:47, 15 July 2017 diff hist +230 SceKernelIntrMgr →Setting up interrupt
- 22:39, 14 July 2017 diff hist +26 Physical Memory
- 12:33, 14 July 2017 diff hist +230 SceExcpmgr →SMC
- 22:29, 13 July 2017 diff hist +172 Caches →PL310 L2 Cache
- 22:25, 13 July 2017 diff hist +407 N Caches Created page with "= PL310 L2 Cache = The Vita uses the [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246f/index.html PL310 r3p1-50rel0] L2 cache (Cache ID Register = 0x410000..."
- 21:59, 13 July 2017 diff hist +45 Main Processor →PL310 L2 Cache
- 15:45, 12 July 2017 diff hist +27 SceSysmem →pOpt->attr bitmask