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[[Category:ARM]]

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...ions is called by the [[Second Loader]], the [[Kernel Boot Loader]] or the ARM [[Kernel]], and unloaded after the call.

Sysroot is a structure for low-level access created when ARM KBL and Kernel are started. Many are pointers to functions or structures th

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...DI0407I_cortex_a9_mpcore_r4p1_trm.pdf ARM Cortex A9 MPcore]. It implements ARM TrustZone for execution in both a non-secure world and a sandboxed [[TrustZ The [[Cmep|cmep processor]] is the actual secure boot device rather than the ARM processor. The cmep processor's boot ROM, nicknamed [[First Loader]], is th

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This module doesn't contain any ARM code; instead, it holds the image for execution on the VENEZIA coprocessor. MeP code parses RPC calls from ARM (issued with <code>sceVeneziaRpcCallGenericThunk()</code> in a function at

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Any device connected to the memory system, such as ARM cores, DMA controllers, LPDDR2... A module that can initiate read and write requests to the interconnect (e.g. ARM cores, DMA, ...).

Requests ARM [[TrustZone]] using [[SMC]] 0x114. [[Category:ARM]]

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....self does not itself run on cmep but only contains encrypted segments for ARM to run. Unless indicated otherwise, all processes are encrypted and require === ARM Secure Kernel ===

@param[in] arm_opcode - Opcode of the ARM instruction that triggered breakpoint (reversed endianness) @param[in] arm_opcode - Opcode of the ARM instruction that triggered breakpoint (reversed endianness)

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...ler is defined in the MPCore TRM [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407i/CACCJFCJ.html]. The PERIPHBASE address (physical) is 0x1A00000 [[Category:ARM]]

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The mailbox is used for communication between ARM [[TrustZone]] and [[Cmep]] ([[Second Loader]] and [[Secure Kernel]]), and w ...t by Cmep to ARM [[TrustZone]] using the lower 16-bits at 0xE0000000. When ARM [[TrustZone]] has read it, the register is set to 0.

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* change ARM clock frequency [[Category:ARM]]

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| ARM cache controller. | ARM Debugger.

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...r a usable buffer overflow in the data section and early code execution on ARM in non-secure privileged mode. ...and ARM TZ ("I am going to reset cmep"). However, as long as both cmep and ARM TZ are pwned post-boot, the second path can be triggered.

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..._loader || Used by first_loader to figure out whether to load from eMMC or ARM comms after reset. Also [[SLSK]] AES Key revision on offset>0x1C-byte>bit:0

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...-a/cortex-a9.php Cortex-A9 MPCore] as its CPU, mounting four little-endian ARM Cortex-A9 processor cores, which is common in modern high performance embed ...2 MiB shared by all cores, while precisely speaking, it's external to the ARM processor core.

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...It initializes ARM [[TrustZone]] (ARM Secure kernel) through [[SKBL]] and ARM Non-secure kernel through [[NSKBL]]. == ARM Kernel BootLoader ==

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...e two big categories of modules on PS Vita: [[PRX]] which are made for the ARM processor and usually are relocatable, and [[Secure Modules]] which are mad

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1) Apply ARM filter. See [[#ARM Filter]]. 2) Remove ARM filter. See [[#ARM Filter]] and [[SKBL#sceArlzArmFilter]].

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| 0x0 || 0x1000 || Miniboot (raw ARM binary) | 0x1000 || Up to 0x7F000 || AES-CBC encrypted stage2 (raw ARM binary)

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/** Structure representing all ARM registers */ [[Category:ARM]]

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ARM kernel module:

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...KU603 JAPAN ARM". PDEL units are labeled "KD77630AF1 EM1-S 1141KU601 JAPAN ARM". Both are likely the same chip from Renesas.

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| ARM Debugger? | Of ARM coprocessor 14?

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The SceCpu libraries provide wrappers for much ARM CP15 co-processor access as well as low level support of spinlocks and othe ...ted in this range. All functions in the Virtual Memory access range run in ARM mode not in Thumb mode.

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Running on ARM Cortex.

// note this same reg is used to enable Cmep reset from arm

| 3.60 || 0x510145F4 || arm [[Category:ARM]]

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...gets its own GPU virtual address space. The MMU tables are managed by the ARM kernel. When a user calls <code>sceGxmMapMemory</code> the kernel first che

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The Non-Secure Kernel Boot Loader (NSKBL) is the first program that runs on ARM cores in Non-Secure state. As its name indicate, it has the role of initial [[Category:ARM]]

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...hardware devices. This provides an additional layer of buffer between the ARM application processor and the CMeP security processor. In addition, since S ...d in the [[Kernel#Security|non-secure kernel]]. This is likely because the ARM secure kernel is only to provide an extra layer of protection to prevent un

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On normal PS Vita boot, ARM resets the cmep processor to load secure_kernel by writing: === Testing half a reset post-secure_kernel operation from ARM ===

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...ind of memory to allocate. Here is a mapping of <code>type</code> flags to ARM MMU flags. Higher bits are used for other options including where to alloca

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Checksum is sent from ARM to Syscon using [[SceSyscon#sceSysconUpdaterExecFinalizeForDriver]]. ...n Ernie firmware shipped with System Software version 3.600.011 but not in ARM update_mgr.skprx.

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...any data leaks. All usermode pointers passed to syscalls are accessed with ARM instructions LDRT and STRT for hardware forced permission checks. Syscalls SMC (Secure Monitor Call) is what allows to interact with ARM [[TrustZone]] from non-secure kernel.

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9 = Shutdown requested. Triggered by ARM ?command? 0x101. ...n, it writes 0x20000 to 0xE0000000. This will either signal ARM or disable ARM communications. Then infinite loop. This is a panic function.

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= ARM TrustZone communication = = ARM Kernel communication =

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On ARM, the [[SceKernelDmacMgr]] module is responsible for commanding the DMACs. | Bigmac || 0xE0050000 || None? || Not visible by ARM NS. Has a key ring.

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...Emulator#Interrupt manager|Interrupt manager]]. Used for MIPS <-> Kermit (ARM) communication ...SRAM. Mapped to [[Physical_Memory#Main_table|<code>0xE8100000</code>]] on ARM side

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You can find an open source ARM TrustZone<->Cmep protocol implementation at https://github.com/xyzz/f00d. I Once result is available, ARM will get an interrupt 201-203. Read status code from 0xE0000004 or 0xE00000

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The UART0 is a debugging console used by ARM, cMep and Syscon. The logic level is 1.8V.

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...kernel. However, this timer's MMIO range is not blacklisted from access by ARM cores in Non-Secure state. An attacker in Non-Secure state can thus change ...and P correspond to the relocation variables detailed in the "ELF for the Arm® Architecture" document.

2: DD2 (VDDA - ARM core, L2 cache) SetArmClockFrequency Finalize Syscon update by sending checksum from ARM to Syscon.

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#define READAS_DEV_UNK 0b10 // masks DRAM and DRAM regs, from ARM bus

...er value for MIPS, TOC address (address of .toc) for PowerPC, always 0 for ARM. | Offset to top of ARM EXIDX (optional)

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[https://developer.arm.com/documentation/ddi0461/b/Programmers-Model/Register-summary CoreSight Tr | 0x3B (ARM)

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...sensitive information in secure world (Sony was wiser here than most other ARM device makers), but the sole task of the secure kernel was to communicate w

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...ectors are copied from TZ memory at 0x40000000 to 0x1F000000 (0x0 alias on ARM). If coldboot, kernel_boot_loader.self is loaded from emmc and decrypted. === Prepares to start ARM ===

| 0.931 || 0x31E10 || ARM | 0.990 || 0x2BF50 || ARM

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In [https://github.com/TheOfficialFloW/Trinity/blob/master/eboot/arm.c#L203 Trinity source code], a module is loaded with flags = 0x10 to bypass [[Category:ARM]]

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...ed that temporarily enable all domains. The access is implemented with the ARM unprivileged access instructions <code>LDRT</code> and <code>STRT</code> to

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#REDIRECT [[ARM Debugger Interface]]

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...SM stored in the [[SLB2]] partition. The raw (encrypted) SELF is stored in ARM [[TrustZone]] memory. It is placed there by an early bootloader. kprx_auth_sm is used to decrypt SELF and SPSFO files for ARM. The CF header is passed into a page aligned buffer and a [[#Physical Addre

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