Physical Memory: Difference between revisions

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Line 560: Line 560:
| ?
| ?
| LPDDR2SUB (config regs) (?)
| LPDDR2SUB (config regs) (?)
|-
| 0xE6000000
| 0xE6008FFF (?)
| ?
| LPDDR2"TOP" (config regs) (?)
|-
|-
| 0xE8000000
| 0xE8000000

Revision as of 07:21, 1 December 2017

Start End Secure Comments
0x00000000 0x00007FFF NS Alias of 0x1F000000, ScePower scratch buffer
0x1A000000 0x1A001FFF NS SceInterruptControllerReg, Interrupts (PERIPHBASE)
0x1A002000 0x1A002FFF ? ScePl310Reg / SceL2CacheReg, L2 Cache Controller
0x1C000000 0x1C1FFFFF NS SceDisplay / SceCameraSRAM (only 960x480 mapped)
0x1F000000 0x1F007FFF NS ScePowerScratchPad32KiB
0x1F840000 0x1F85FFFF NS SceVeneziaSpram
0x20000000 0x27FFFFFF NS VRAM
0x40000000 0x401FFFFF S Secure DRAM (extra 1 meg before FW 3.52)
0x40200000 0x5FCFFFFF NS Shared DRAM (starts at 0x40300000 before FW 3.52)
0x60000000 0x7FFFFFFF NS Devkit additional DRAM
0x80000000 0x9FFFFFFF NS Unused or DRAM ?
0xE0000000 ? S F00D Processor
0xE0100000 0xE0100FFF NS SceGpio1Reg
0xE0400000 0xE0400FFF NS SceDmacmgrDmac4Reg
0xE0410000 0xE0410FFF NS SceDmacmgrDmac5Reg
0xE0420000 0xE0420FFF NS SceI2s0Reg
0xE0430000 0xE0430FFF NS SceI2s1Reg
0xE0440000 0xE0440FFF NS SceI2s2Reg
0xE0450000 0xE0450FFF NS SceI2s3Reg
0xE0460000 0xE0460FFF NS SceI2s5Reg
0xE0470000 0xE0470FFF NS SceI2s4Reg
0xE0490000 0xE0490FFF NS SceI2s7Reg
0xE04A0000 0xE04A0FFF NS SceSrcMix0Reg
0xE04B0000 0xE04B0FFF NS SceSrcMix1Reg
0xE04C0000 0xE04C0FFF NS SceSrcMix2Reg
0xE04D0000 0xE04D3FFF NS SceSpdifReg
0xE04DC000 0xE04DCFFF NS SceAclkgenReg
0xE04E0000 0xE04E0FFF NS SceDmacmgrKeyringReg / SceSblDMAC5DmacKRBase
0xE0500000 0xE0500FFF NS SceI2c0Reg
0xE0510000 0xE0510FFF NS SceI2c1Reg
0xE0900000 0xE0900FFF NS SceMsif
0xE0A00000 0xE0A00FFF NS SceSpi0Reg (SceSyscon)
0xE0A10000 0xE0A10FFF NS SceSpi1Reg (SceMotionDev)
0xE0A20000 0xE0A20FFF NS SceSpi2Reg (SceOled)
0xE0B00000 0xE0B00FFF NS SceSdif0
0xE0C00000 0xE0C00FFF NS SceSdif1
0xE0C10000 0xE0C10FFF NS SceSdif2
0xE0C20000 ? ? SceSdif3 (not present on 1.69)
0xE2030000 0xE209FFFF NS SceUartReg
0xE20A0000 0xE20A0FFF NS SceGpio0Reg / SceLedReg
0xE20A1000 0xE20AFFFF NS SceLedReg
0xE20B1000 0xE20B5FFF NS SceLongRangeTimerReg
0xE20B6000 0xE20B6003 NS Clock in usec
0xE20B7000 0xE20BFFFF NS SceWordTimerReg
0xE20BE000 0xE20BEFFF ? Timer for usleep
0xE20C0000 0xE20C0FFF NS ScePwmReg
0xE3000000 0xE3000FFF NS SceDmacmgrDmac0Reg
0xE3010000 0xE3010FFF NS SceDmacmgrDmac1Reg
0xE3020000 0xE3020FFF NS SceCif0Reg
0xE3030000 0xE3030FFF NS SceCif1Reg
0xE3050000 0xE3050FFF NS SceCsi0Reg
0xE3060000 0xE3060FFF NS SceCsi1Reg
0xE3100000 0xE3100FFF NS ScePervasiveMisc
0xE3101000 0xE3101FFF NS ScePervasiveResetReg
0xE3102000 0xE3102FFF NS ScePervasiveGate
0xE3103000 0xE3103FFF NS ScePervasiveBaseClk
0xE3104000 0xE3104FFF NS ScePervasiveVid
0xE3105000 0xE3105FFF NS SceUartClkgenReg
0xE3106000 0xE3106FFF NS ScePervasiveMailboxReg
0xE3108000 0xE3108FFF NS ScePervasiveTas0
0xE3109000 0xE3109FFF NS ScePervasiveTas1
0xE310A000 0xE310AFFF NS ScePervasiveTas2
0xE310B000 0xE310BFFF NS ScePervasiveTas3
0xE310C000 0xE310CFFF NS ScePervasiveTas4
0xE310D000 0xE310DFFF NS ScePervasiveTas5
0xE310E000 0xE310EFFF NS ScePervasiveTas6
0xE310F000 0xE310FFFF NS ScePervasiveTas7
0xE3110000 0xE3110FFF NS SceUdcd0 / ScePervasive2Reg
0xE3200000 0xE3200FFF S Base Debug ROM Table
0xE3203000 0xE3203FFF NS SceTpiuReg
0xE3204000 0xE3204FFF NS SceFunnelReg
0xE3205000 0xE3205FFF NS SceItmReg
0xE3300000 0xE3300FFF S Cortex A9 Debug ROM Table
0xE3310000 0xE3310FFF NS SceDbg0Reg, Debugger Interface
0xE3311000 0xE3311FFF NS ScePmu0Reg
0xE3312000 0xE3312FFF NS SceDbg1Reg, Debugger Interface
0xE3313000 0xE3313FFF NS ScePmu1Reg
0xE3314000 0xE3314FFF NS SceDbg2Reg, Debugger Interface
0xE3315000 0xE3315FFF NS ScePmu2Reg
0xE3316000 0xE3316FFF NS SceDbg3Reg, Debugger Interface
0xE3317000 0xE3317FFF NS ScePmu3Reg
0xE3318000 0xE3318FFF NS SceCti0Reg
0xE3319000 0xE3319FFF NS SceCti1Reg
0xE331A000 0xE331AFFF NS SceCti2Reg
0xE331B000 0xE331BFFF NS SceCti3Reg
0xE331C000 0xE331CFFF NS ScePtm0Reg
0xE331D000 0xE331DFFF NS ScePtm1Reg
0xE331E000 0xE331EFFF NS ScePtm2Reg
0xE331F000 0xE331FFFF NS ScePtm3Reg
0xE3320000 0xE3323FFF NS SceIntrmgrVfpIntRegs
0xE4020000 0xE4020FFF NS SceUsbdEhci
0xE40B0000 0xE40B0FFF NS SceUsbdEhci
0xE40C0000 0xE40C0FFF NS SceUdcd1
0xE40D0000 0xE40D0FFF NS SceUdcd2
0xE40E0000 0xE40E0FFF NS SceUsbdEhci
0xE5000000 0xE5000FFF NS SceDmacmgrDmac2Reg
0xE5010000 0xE5010FFF NS SceDmacmgrDmac3Reg
0xE5020000 0xE5020FFF NS SceIftu0RegA (OLED FB)
0xE5021000 0xE5021FFF NS SceIftu0RegB
0xE5022000 0xE5022FFF NS SceIftuc0Reg
0xE5030000 0xE5030FFF NS SceIftu1RegA (HDMI FB)
0xE5031000 0xE5031FFF NS SceIftu1RegB
0xE5032000 0xE5032FFF NS SceIftuc1Reg
0xE5040000 0xE5040FFF NS SceIftu2Reg
0xE5050000 0xE5050FFF NS SceDsi0Reg
0xE5060000 0xE5060FFF NS SceDsi1Reg
0xE5070000 0xE5070FFF NS SceCompatMailbox
0xE5071000 0xE5071FFF NS SceCompatLCDDMA
0xE50C0000 0xE50C0FFF NS SceDmacmgrDmac6Reg
0xE50D0000 0xE50D1FFF NS ScePfmReg
0xE5880000 0xE5888FFF (?) ? LPDDR2SUB (config regs) (?)
0xE6000000 0xE6008FFF (?) ? LPDDR2"TOP" (config regs) (?)
0xE8000000 0xE8001FFF S SceSonyRegbus
0xE8100000 0xE8100FFF NS SceCompatSharedSram (0xBFC00000 in PSP)
0xE8200000 0xE8200FFF S SceEmcTop
0xE8300000 0xE8301FFF S SceGrab
0xE8400000 0xE841FFFF NS SceSGX543Reg
0xEC000000 ? ? ?