User contributions for Xerpi
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15 July 2017
- 23:3223:32, 15 July 2017 diff hist +80 SceExcpmgr →SMC calls
- 23:2423:24, 15 July 2017 diff hist +192 SceExcpmgr →SMC calls
- 23:2023:20, 15 July 2017 diff hist +3 Pervasive →Devices
- 22:4322:43, 15 July 2017 diff hist +3 ScePower →scePowerSetGpuClockFrequency
- 22:4222:42, 15 July 2017 diff hist +22 ScePower →scePowerSetGpuClockFrequency
- 17:5117:51, 15 July 2017 diff hist +130 SceExcpmgr →SMC calls
- 17:4917:49, 15 July 2017 diff hist +83 SceExcpmgr →SMC calls
- 16:5116:51, 15 July 2017 diff hist +137 SceExcpmgr →SMC calls
- 16:4916:49, 15 July 2017 diff hist +179 SceSysmem →SceCpuForKernel
- 15:5115:51, 15 July 2017 diff hist +283 SceExcpmgr →SMC calls
- 13:2213:22, 15 July 2017 diff hist +8 SceExcpmgr →SMC calls
- 13:2113:21, 15 July 2017 diff hist +37 SceExcpmgr →SMC calls
- 08:5108:51, 15 July 2017 diff hist +34 SceKernelIntrMgr →Setting up interrupt
- 08:4708:47, 15 July 2017 diff hist +230 SceKernelIntrMgr →Setting up interrupt
14 July 2017
- 22:3922:39, 14 July 2017 diff hist +26 Physical Memory No edit summary
- 12:3312:33, 14 July 2017 diff hist +230 SceExcpmgr →SMC
13 July 2017
- 22:2922:29, 13 July 2017 diff hist +172 Caches →PL310 L2 Cache
- 22:2522:25, 13 July 2017 diff hist +407 N Caches Created page with "= PL310 L2 Cache = The Vita uses the [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246f/index.html PL310 r3p1-50rel0] L2 cache (Cache ID Register = 0x410000..."
- 21:5921:59, 13 July 2017 diff hist +45 Main Processor →PL310 L2 Cache
12 July 2017
- 15:4515:45, 12 July 2017 diff hist +27 SceSysmem →pOpt->attr bitmask
- 13:0313:03, 12 July 2017 diff hist +2 SceSysmem →SceSysmemForKernel
- 13:0113:01, 12 July 2017 diff hist +332 SceSysmem →sceKernelAllocMemBlockForKernel
- 11:1211:12, 12 July 2017 diff hist +18 Pervasive →Misc
- 11:1111:11, 12 July 2017 diff hist +245 Pervasive No edit summary
- 08:3508:35, 12 July 2017 diff hist +40 SceSyscon →Callbacks
11 July 2017
- 23:1523:15, 11 July 2017 diff hist +44 SceKernelIntrMgr →Registered Subinterrupts
- 22:2922:29, 11 July 2017 diff hist +20 SceSyscon →Callbacks
- 22:0922:09, 11 July 2017 diff hist +14 SceSyscon →Reset device
- 22:0622:06, 11 July 2017 diff hist +22 SceSyscon →Reset device
- 21:4621:46, 11 July 2017 diff hist +64 SceSyscon →Reset device
- 21:3821:38, 11 July 2017 diff hist +22 SceSyscon →Reset device
- 21:2921:29, 11 July 2017 diff hist +102 ScePower →ScePowerForDriver
- 16:5816:58, 11 July 2017 diff hist +1,080 SceLowio →ScePervasiveForDriver
10 July 2017
- 23:5123:51, 10 July 2017 diff hist +22 I2C Registers →Registers
- 22:4922:49, 10 July 2017 diff hist +7 I2C Registers →Registers
- 22:4822:48, 10 July 2017 diff hist +24 I2C Registers →Registers
- 12:3312:33, 10 July 2017 diff hist +24 UART Console →UART Initialization
- 12:2912:29, 10 July 2017 diff hist +320 UART Console No edit summary
- 12:2612:26, 10 July 2017 diff hist +24 UART Console →PlayStation TV UART0 location
- 12:2512:25, 10 July 2017 diff hist +29 N File:Pstv uart0.png PlayStation TV UART0 location
- 12:2212:22, 10 July 2017 diff hist +23 Template:Devices No edit summary
- 12:2012:20, 10 July 2017 diff hist +62 UART Console No edit summary
- 12:1912:19, 10 July 2017 diff hist +6 SceLowio →ScePervasiveForDriver
- 12:1812:18, 10 July 2017 diff hist +33 N UART Console Created page with "The UART0 is a debugging console."
- 12:1712:17, 10 July 2017 diff hist +8 SceLowio →ScePervasiveForDriver_A7CE7DCC
- 12:1312:13, 10 July 2017 diff hist +10 Pervasive →Devices
8 July 2017
- 22:3722:37, 8 July 2017 diff hist +12 I2C Registers →I2C Devices
- 22:0222:02, 8 July 2017 diff hist +40 I2C Registers →I2C Devices
- 21:5521:55, 8 July 2017 diff hist +28 I2C Registers →I2C Devices
- 21:5121:51, 8 July 2017 diff hist +28 I2C Registers →I2C Devices